[MIPS] MT: Improved multithreading support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
@@ -14,9 +14,14 @@
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#include <linux/threads.h>
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/mipsregs.h>
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#include <asm/asm-offsets.h>
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#ifdef CONFIG_MIPS_MT_SMTC
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#include <asm/mipsmtregs.h>
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#endif /* CONFIG_MIPS_MT_SMTC */
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.macro SAVE_AT
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.set push
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.set noat
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@@ -57,13 +62,30 @@
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#ifdef CONFIG_SMP
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.macro get_saved_sp /* SMP variation */
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#ifdef CONFIG_32BIT
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#ifdef CONFIG_MIPS_MT_SMTC
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.set mips32
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mfc0 k0, CP0_TCBIND;
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.set mips0
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lui k1, %hi(kernelsp)
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srl k0, k0, 19
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/* No need to shift down and up to clear bits 0-1 */
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#else
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mfc0 k0, CP0_CONTEXT
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lui k1, %hi(kernelsp)
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srl k0, k0, 23
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#endif
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addu k1, k0
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LONG_L k1, %lo(kernelsp)(k1)
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#endif
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#ifdef CONFIG_64BIT
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#ifdef CONFIG_MIPS_MT_SMTC
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.set mips64
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mfc0 k0, CP0_TCBIND;
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.set mips0
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lui k0, %highest(kernelsp)
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dsrl k1, 19
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/* No need to shift down and up to clear bits 0-2 */
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#else
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MFC0 k1, CP0_CONTEXT
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lui k0, %highest(kernelsp)
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dsrl k1, 23
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@@ -71,19 +93,30 @@
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dsll k0, k0, 16
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daddiu k0, %hi(kernelsp)
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dsll k0, k0, 16
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#endif /* CONFIG_MIPS_MT_SMTC */
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daddu k1, k1, k0
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LONG_L k1, %lo(kernelsp)(k1)
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#endif
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#endif /* CONFIG_64BIT */
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.endm
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.macro set_saved_sp stackp temp temp2
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#ifdef CONFIG_32BIT
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#ifdef CONFIG_MIPS_MT_SMTC
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mfc0 \temp, CP0_TCBIND
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srl \temp, 19
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#else
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mfc0 \temp, CP0_CONTEXT
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srl \temp, 23
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#endif
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#endif
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#ifdef CONFIG_64BIT
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#ifdef CONFIG_MIPS_MT_SMTC
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mfc0 \temp, CP0_TCBIND
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dsrl \temp, 19
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#else
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MFC0 \temp, CP0_CONTEXT
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dsrl \temp, 23
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#endif
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#endif
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LONG_S \stackp, kernelsp(\temp)
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.endm
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@@ -122,10 +155,25 @@
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PTR_SUBU sp, k1, PT_SIZE
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LONG_S k0, PT_R29(sp)
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LONG_S $3, PT_R3(sp)
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/*
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* You might think that you don't need to save $0,
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* but the FPU emulator and gdb remote debug stub
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* need it to operate correctly
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*/
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LONG_S $0, PT_R0(sp)
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mfc0 v1, CP0_STATUS
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LONG_S $2, PT_R2(sp)
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LONG_S v1, PT_STATUS(sp)
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* Ideally, these instructions would be shuffled in
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* to cover the pipeline delay.
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*/
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.set mips32
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mfc0 v1, CP0_TCSTATUS
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.set mips0
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LONG_S v1, PT_TCSTATUS(sp)
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#endif /* CONFIG_MIPS_MT_SMTC */
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LONG_S $4, PT_R4(sp)
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mfc0 v1, CP0_CAUSE
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LONG_S $5, PT_R5(sp)
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@@ -234,14 +282,36 @@
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.endm
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#else
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/*
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* For SMTC kernel, global IE should be left set, and interrupts
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* controlled exclusively via IXMT.
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*/
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#ifdef CONFIG_MIPS_MT_SMTC
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#define STATMASK 0x1e
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#else
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#define STATMASK 0x1f
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#endif
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.macro RESTORE_SOME
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.set push
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.set reorder
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.set noat
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#ifdef CONFIG_MIPS_MT_SMTC
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.set mips32r2
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/*
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* This may not really be necessary if ints are already
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* inhibited here.
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*/
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mfc0 v0, CP0_TCSTATUS
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ori v0, TCSTATUS_IXMT
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mtc0 v0, CP0_TCSTATUS
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ehb
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DMT 5 # dmt a1
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jal mips_ihb
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#endif /* CONFIG_MIPS_MT_SMTC */
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mfc0 a0, CP0_STATUS
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ori a0, 0x1f
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xori a0, 0x1f
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ori a0, STATMASK
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xori a0, STATMASK
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mtc0 a0, CP0_STATUS
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li v1, 0xff00
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and a0, v1
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@@ -250,6 +320,26 @@
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and v0, v1
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or v0, a0
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mtc0 v0, CP0_STATUS
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* Only after EXL/ERL have been restored to status can we
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* restore TCStatus.IXMT.
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*/
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LONG_L v1, PT_TCSTATUS(sp)
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ehb
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mfc0 v0, CP0_TCSTATUS
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andi v1, TCSTATUS_IXMT
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/* We know that TCStatua.IXMT should be set from above */
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xori v0, v0, TCSTATUS_IXMT
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or v0, v0, v1
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mtc0 v0, CP0_TCSTATUS
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ehb
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andi a1, a1, VPECONTROL_TE
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beqz a1, 1f
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emt
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1:
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.set mips0
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#endif /* CONFIG_MIPS_MT_SMTC */
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LONG_L v1, PT_EPC(sp)
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MTC0 v1, CP0_EPC
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LONG_L $31, PT_R31(sp)
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@@ -302,11 +392,33 @@
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* Set cp0 enable bit as sign that we're running on the kernel stack
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*/
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.macro CLI
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#if !defined(CONFIG_MIPS_MT_SMTC)
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU0 | 0x1f
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or t0, t1
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xori t0, 0x1f
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mtc0 t0, CP0_STATUS
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#else /* CONFIG_MIPS_MT_SMTC */
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/*
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* For SMTC, we need to set privilege
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* and disable interrupts only for the
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* current TC, using the TCStatus register.
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*/
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mfc0 t0,CP0_TCSTATUS
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/* Fortunately CU 0 is in the same place in both registers */
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/* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
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li t1, ST0_CU0 | 0x08001c00
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or t0,t1
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/* Clear TKSU, leave IXMT */
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xori t0, 0x00001800
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mtc0 t0, CP0_TCSTATUS
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ehb
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/* We need to leave the global IE bit set, but clear EXL...*/
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mfc0 t0, CP0_STATUS
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ori t0, ST0_EXL | ST0_ERL
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xori t0, ST0_EXL | ST0_ERL
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mtc0 t0, CP0_STATUS
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#endif /* CONFIG_MIPS_MT_SMTC */
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irq_disable_hazard
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.endm
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@@ -315,11 +427,35 @@
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* Set cp0 enable bit as sign that we're running on the kernel stack
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*/
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.macro STI
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#if !defined(CONFIG_MIPS_MT_SMTC)
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU0 | 0x1f
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or t0, t1
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xori t0, 0x1e
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mtc0 t0, CP0_STATUS
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#else /* CONFIG_MIPS_MT_SMTC */
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/*
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* For SMTC, we need to set privilege
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* and enable interrupts only for the
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* current TC, using the TCStatus register.
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*/
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ehb
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mfc0 t0,CP0_TCSTATUS
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/* Fortunately CU 0 is in the same place in both registers */
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/* Set TCU0, TKSU (for later inversion) and IXMT */
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li t1, ST0_CU0 | 0x08001c00
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or t0,t1
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/* Clear TKSU *and* IXMT */
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xori t0, 0x00001c00
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mtc0 t0, CP0_TCSTATUS
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ehb
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/* We need to leave the global IE bit set, but clear EXL...*/
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mfc0 t0, CP0_STATUS
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ori t0, ST0_EXL
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xori t0, ST0_EXL
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mtc0 t0, CP0_STATUS
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/* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
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#endif /* CONFIG_MIPS_MT_SMTC */
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irq_enable_hazard
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.endm
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@@ -328,11 +464,56 @@
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* Set cp0 enable bit as sign that we're running on the kernel stack
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*/
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.macro KMODE
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* This gets baroque in SMTC. We want to
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* protect the non-atomic clearing of EXL
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* with DMT/EMT, but we don't want to take
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* an interrupt while DMT is still in effect.
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*/
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/* KMODE gets invoked from both reorder and noreorder code */
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.set push
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.set mips32r2
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.set noreorder
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mfc0 v0, CP0_TCSTATUS
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andi v1, v0, TCSTATUS_IXMT
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ori v0, TCSTATUS_IXMT
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mtc0 v0, CP0_TCSTATUS
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ehb
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DMT 2 # dmt v0
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/*
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* We don't know a priori if ra is "live"
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*/
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move t0, ra
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jal mips_ihb
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nop /* delay slot */
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move ra, t0
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#endif /* CONFIG_MIPS_MT_SMTC */
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU0 | 0x1e
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or t0, t1
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xori t0, 0x1e
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mtc0 t0, CP0_STATUS
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#ifdef CONFIG_MIPS_MT_SMTC
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ehb
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andi v0, v0, VPECONTROL_TE
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beqz v0, 2f
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nop /* delay slot */
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emt
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2:
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mfc0 v0, CP0_TCSTATUS
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/* Clear IXMT, then OR in previous value */
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ori v0, TCSTATUS_IXMT
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xori v0, TCSTATUS_IXMT
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or v0, v1, v0
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mtc0 v0, CP0_TCSTATUS
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/*
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* irq_disable_hazard below should expand to EHB
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* on 24K/34K CPUS
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*/
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.set pop
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#endif /* CONFIG_MIPS_MT_SMTC */
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irq_disable_hazard
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.endm
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