Merge tag 'drm-intel-next-2020-07-15' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
drm/i915 features for v5.9, batch #2 Highlights: - Very early DG1 enabling (Abdiel, Lucas, Anusha) Gem/GT: - Fix spinlock recursion on signaling a signaled request (Chris) - Perf: Use GTT when saving/restoring engine GPR (Umesh Nerlige Ramappa) - SSEU refactoring, debugfs move under gt/ (Daniele, Venkata Sandeep Dhanalakota) - Various GT refactoring and cleanup, preparation for future changes (Daniele) - Adjust HuC state accordingly after GuC fetch error (Michał Winiarski) - UC debugfs updates (Michał Winiarski) - Only revoke the GGTT mmappings on aperture detiling changes (Chris) - Only revoke mmap handlers if active (Chris) - Split the context's obj:vma lut into its own mutex (Chris) - Various memory, mmap and performance optimisations (Chris) - Improve system stability in case of false CS events (Chris) - Various refactorings and cleanup (Chris) - Always reset the engine on execlist failures (Chris) - Trace placement of timeline HWSP (Chris) - Update dma-attributes for our sg DMA (Chris) Display: - TGL CDCLK workaround tweaks to unbreak 8K display support (Stanislav) - A number of FBC fixes, along with i865 FBC enabling (Ville) - Validate MST modes against PBN limits (Lyude, Shawn Lee) - Do not access non-existing swizzle registers (Lucas) - Revert GEN11+ HBR3 rate fix that caused issues on TGL (Matt Atwood) - Update TGL+ combo phy initialization to match spec update (José) - Fix HDCP Content Protection property state machine (Anshuman) - Fix HDCP revoked keys handling (Ram) - Improve DDI BUF status checks and waits (Manasi) - Various SDVO+HDMI+DVI fixes around colorimetry, clocking, pixel repeat etc. (Ville) - DP voltage swing function refactoring (José) - WARN if max vswing/pre-emphasis violates the DP spec (Ville) Other: - Add new EHL PCI IDs (José) - Unify struct intel_digital_port variable naming (Lucas) - Various taint updates to aid debugging and improve CI (Michał Winiarski) - Straggler conversions to new mmio register accessors (Daniele) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87a70029vz.fsf@intel.com
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@@ -968,6 +968,48 @@ struct drm_connector_helper_funcs {
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*/
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enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
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struct drm_display_mode *mode);
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/**
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* @mode_valid_ctx:
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*
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* Callback to validate a mode for a connector, irrespective of the
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* specific display configuration.
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*
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* This callback is used by the probe helpers to filter the mode list
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* (which is usually derived from the EDID data block from the sink).
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* See e.g. drm_helper_probe_single_connector_modes().
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*
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* This function is optional, and is the atomic version of
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* &drm_connector_helper_funcs.mode_valid.
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*
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* To allow for accessing the atomic state of modesetting objects, the
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* helper libraries always call this with ctx set to a valid context,
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* and &drm_mode_config.connection_mutex will always be locked with
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* the ctx parameter set to @ctx. This allows for taking additional
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* locks as required.
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*
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* Even though additional locks may be acquired, this callback is
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* still expected not to take any constraints into account which would
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* be influenced by the currently set display state - such constraints
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* should be handled in the driver's atomic check. For example, if a
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* connector shares display bandwidth with other connectors then it
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* would be ok to validate the minimum bandwidth requirement of a mode
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* against the maximum possible bandwidth of the connector. But it
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* wouldn't be ok to take the current bandwidth usage of other
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* connectors into account, as this would change depending on the
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* display state.
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*
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* Returns:
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* 0 if &drm_connector_helper_funcs.mode_valid_ctx succeeded and wrote
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* the &enum drm_mode_status value to @status, or a negative error
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* code otherwise.
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*
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*/
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int (*mode_valid_ctx)(struct drm_connector *connector,
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struct drm_display_mode *mode,
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struct drm_modeset_acquire_ctx *ctx,
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enum drm_mode_status *status);
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/**
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* @best_encoder:
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*
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@@ -588,7 +588,11 @@
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INTEL_VGA_DEVICE(0x4551, info), \
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INTEL_VGA_DEVICE(0x4541, info), \
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INTEL_VGA_DEVICE(0x4E71, info), \
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INTEL_VGA_DEVICE(0x4557, info), \
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INTEL_VGA_DEVICE(0x4555, info), \
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INTEL_VGA_DEVICE(0x4E61, info), \
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INTEL_VGA_DEVICE(0x4E57, info), \
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INTEL_VGA_DEVICE(0x4E55, info), \
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INTEL_VGA_DEVICE(0x4E51, info)
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/* TGL */
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@@ -614,4 +618,8 @@
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INTEL_VGA_DEVICE(0x4C90, info), \
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INTEL_VGA_DEVICE(0x4C9A, info)
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/* DG1 */
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#define INTEL_DG1_IDS(info) \
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INTEL_VGA_DEVICE(0x4905, info)
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#endif /* _I915_PCIIDS_H */
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