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mtd: spi-nor: Check bus width while setting QE bit

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[ Upstream commit f01d8155a92e33cdaa85d20bfbe6c441907b3c1f ]

spi_nor_write_16bit_sr_and_check() should also check if bus width is
4 before setting QE bit.

Fixes: 39d1e3340c ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()")
Suggested-by: Michael Walle <michael@walle.cc>
Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20230818064524.1229100-2-hsinyi@chromium.org
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Hsin-Yi Wang
2023-08-18 14:42:23 +08:00
committed by Greg Kroah-Hartman
parent 71ac2ffd7f
commit 40d8f9bffe
1 changed files with 10 additions and 9 deletions
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19
drivers/mtd/spi-nor/core.c
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@@ -800,21 +800,22 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
ret = spi_nor_read_cr(nor, &sr_cr[1]); ret = spi_nor_read_cr(nor, &sr_cr[1]);
if (ret) if (ret)
return ret; return ret;
} else if (nor->params->quad_enable) { } else if (spi_nor_get_protocol_width(nor->read_proto) == 4 &&
spi_nor_get_protocol_width(nor->write_proto) == 4 &&
nor->params->quad_enable) {
/* /*
* If the Status Register 2 Read command (35h) is not * If the Status Register 2 Read command (35h) is not
* supported, we should at least be sure we don't * supported, we should at least be sure we don't
* change the value of the SR2 Quad Enable bit. * change the value of the SR2 Quad Enable bit.
* *
* We can safely assume that when the Quad Enable method is * When the Quad Enable method is set and the buswidth is 4, we
* set, the value of the QE bit is one, as a consequence of the * can safely assume that the value of the QE bit is one, as a
* nor->params->quad_enable() call. * consequence of the nor->params->quad_enable() call.
* *
* We can safely assume that the Quad Enable bit is present in * According to the JESD216 revB standard, BFPT DWORDS[15],
* the Status Register 2 at BIT(1). According to the JESD216 * bits 22:20, the 16-bit Write Status (01h) command is
* revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit * available just for the cases in which the QE bit is
* Write Status (01h) command is available just for the cases * described in SR2 at BIT(1).
* in which the QE bit is described in SR2 at BIT(1).
*/ */
sr_cr[1] = SR2_QUAD_EN_BIT1; sr_cr[1] = SR2_QUAD_EN_BIT1;
} else { } else {