Merge tag 'drm-intel-next-2014-09-05' of git://anongit.freedesktop.org/drm-intel into drm-next
- final bits (again) for the rotation support (Sonika Jindal) - support bl_power in the intel backlight (Jani) - vdd handling improvements from Ville - i830M fixes from Ville - piles of prep work all over to make skl enabling just plug in (Damien, Sonika) - rename DP training defines to reflect latest edp standards, this touches all drm drivers supporting DP (Sonika Jindal) - cache edids during single detect cycle to avoid re-reading it for e.g. audio, from Chris - move w/a for registers which are stored in the hw context to the context init code (Arun&Damien) - edp panel power sequencer fixes, helps chv a lot (Ville) - piles of other chv fixes all over - much more paranoid pageflip handling with stall detection and better recovery from Chris - small things all over, as usual * tag 'drm-intel-next-2014-09-05' of git://anongit.freedesktop.org/drm-intel: (114 commits) drm/i915: Update DRIVER_DATE to 20140905 drm/i915: Decouple the stuck pageflip on modeset drm/i915: Check for a stalled page flip after each vblank drm/i915: Introduce a for_each_plane() macro drm/i915: Rewrite ABS_DIFF() in a safer manner drm/i915: Add comments explaining the vdd on/off functions drm/i915: Move DP port disable to post_disable for pch platforms drm/i915: Enable DP port earlier drm/i915: Turn on panel power before doing aux transfers drm/i915: Be more careful when picking the initial power sequencer pipe drm/i915: Reset power sequencer pipe tracking when disp2d is off drm/i915: Track which port is using which pipe's power sequencer drm/i915: Fix edp vdd locking drm/i915: Reset the HEAD pointer for the ring after writing START drm/i915: Fix unsafe vma iteration in i915_drop_caches drm/i915: init sprites with univeral plane init function drm/i915: Check of !HAS_PCH_SPLIT() in PCH transcoder funcs drm/i915: Use HAS_GMCH_DISPLAY un underrun reporting code drm/i915: Use IS_BROADWELL() instead of IS_GEN8() in forcewake code drm/i915: Don't call gen8_fbc_sw_flush() on chv ...
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@@ -1085,7 +1085,13 @@ i915_gem_check_wedge(struct i915_gpu_error *error,
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if (i915_terminally_wedged(error))
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return -EIO;
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return -EAGAIN;
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/*
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* Check if GPU Reset is in progress - we need intel_ring_begin
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* to work properly to reinit the hw state while the gpu is
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* still marked as reset-in-progress. Handle this with a flag.
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*/
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if (!error->reload_in_reset)
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return -EAGAIN;
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}
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return 0;
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@@ -2982,9 +2988,11 @@ int i915_gpu_idle(struct drm_device *dev)
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/* Flush everything onto the inactive list. */
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for_each_ring(ring, dev_priv, i) {
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ret = i915_switch_context(ring, ring->default_context);
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if (ret)
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return ret;
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if (!i915.enable_execlists) {
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ret = i915_switch_context(ring, ring->default_context);
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if (ret)
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return ret;
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}
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ret = intel_ring_idle(ring);
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if (ret)
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@@ -4658,11 +4666,46 @@ intel_enable_blt(struct drm_device *dev)
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return true;
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}
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static void init_unused_ring(struct drm_device *dev, u32 base)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_WRITE(RING_CTL(base), 0);
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I915_WRITE(RING_HEAD(base), 0);
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I915_WRITE(RING_TAIL(base), 0);
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I915_WRITE(RING_START(base), 0);
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}
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static void init_unused_rings(struct drm_device *dev)
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{
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if (IS_I830(dev)) {
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init_unused_ring(dev, PRB1_BASE);
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init_unused_ring(dev, SRB0_BASE);
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init_unused_ring(dev, SRB1_BASE);
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init_unused_ring(dev, SRB2_BASE);
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init_unused_ring(dev, SRB3_BASE);
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} else if (IS_GEN2(dev)) {
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init_unused_ring(dev, SRB0_BASE);
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init_unused_ring(dev, SRB1_BASE);
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} else if (IS_GEN3(dev)) {
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init_unused_ring(dev, PRB1_BASE);
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init_unused_ring(dev, PRB2_BASE);
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}
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}
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int i915_gem_init_rings(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret;
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/*
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* At least 830 can leave some of the unused rings
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* "active" (ie. head != tail) after resume which
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* will prevent c3 entry. Makes sure all unused rings
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* are totally idle.
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*/
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init_unused_rings(dev);
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ret = intel_init_render_ring_buffer(dev);
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if (ret)
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return ret;
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