Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner: "The irq departement delivers: - plug a potential race related to chained interrupt handlers - core updates which address the needs of the x86 irqdomain conversion - new irqchip callback to support affinity settings for VCPUs - the usual pile of updates to interrupt chip drivers - a few helper functions to allow further cleanups and simplifications I have a largish pile of coccinelle scripted/verified cleanups and simplifications pending on top of that, but I prefer to send that towards the end of the merge window when the arch/driver changes have hit your tree to avoid API change wreckage as far as possible" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (34 commits) genirq: Remove bogus restriction in irq_move_mask_irq() irqchip: atmel-aic5: Add sama5d2 support irq: spear-shirq: Fix race in installing chained IRQ handler irq: irq-keystone: Fix race in installing chained IRQ handler gpio: gpio-tegra: Fix race in installing chained IRQ handler gpio: gpio-mxs: Fix race in installing chained IRQ handler gpio: gpio-mxc: Fix race in installing chained IRQ handler ARM: gemini: Fix race in installing GPIO chained IRQ handler GPU: ipu: Fix race in installing IPU chained IRQ handler ARM: sa1100: convert SA11x0 related code to use new chained handler helper irq: Add irq_set_chained_handler_and_data() irqchip: exynos-combiner: Save IRQ enable set on suspend genirq: Introduce helper function irq_data_get_affinity_mask() genirq: Introduce helper function irq_data_get_node() genirq: Introduce struct irq_common_data to host shared irq data genirq: Prevent crash in irq_move_irq() genirq: Enhance irq_data_to_desc() to support hierarchy irqdomain irqchip: gic: Simplify gic_configure_irq by using IRQCHIP_SET_TYPE_MASKED irqchip: renesas: intc-irqpin: Improve binding documentation genirq: Set IRQCHIP_SKIP_SET_WAKE for no_irq_chip ...
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@@ -437,14 +437,13 @@ static int mxc_gpio_probe(struct platform_device *pdev)
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irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
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} else {
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/* setup one handler for each entry */
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irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
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irq_set_handler_data(port->irq, port);
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if (port->irq_high > 0) {
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irq_set_chained_handler_and_data(port->irq,
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mx3_gpio_irq_handler, port);
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if (port->irq_high > 0)
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/* setup handler for GPIO 16 to 31 */
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irq_set_chained_handler(port->irq_high,
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mx3_gpio_irq_handler);
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irq_set_handler_data(port->irq_high, port);
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}
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irq_set_chained_handler_and_data(port->irq_high,
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mx3_gpio_irq_handler,
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port);
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}
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err = bgpio_init(&port->bgc, &pdev->dev, 4,
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@@ -320,8 +320,8 @@ static int mxs_gpio_probe(struct platform_device *pdev)
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mxs_gpio_init_gc(port, irq_base);
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/* setup one handler for each entry */
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irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
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irq_set_handler_data(port->irq, port);
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irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
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port);
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err = bgpio_init(&port->bgc, &pdev->dev, 4,
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port->base + PINCTRL_DIN(port),
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@@ -515,8 +515,8 @@ static int tegra_gpio_probe(struct platform_device *pdev)
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for (i = 0; i < tegra_gpio_bank_count; i++) {
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bank = &tegra_gpio_banks[i];
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irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
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irq_set_handler_data(bank->irq, bank);
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irq_set_chained_handler_and_data(bank->irq,
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tegra_gpio_irq_handler, bank);
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for (j = 0; j < 4; j++)
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spin_lock_init(&bank->lvl_lock[j]);
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