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Merge tag 'qcom-dt-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into for-next

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Merge "Qualcomm ARM Based Device Tree Updates for v3.16" from Kumar Gala:

* Added device tree nodes for pinctrl and SDHC for msm8974 SoC/DB8074 board
* Added binding spec for GSBI configuration node

* tag 'qcom-dt-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
  soc: qcom: Add device tree binding for GSBI
  ARM: dts: msm: Add SDHC controller nodes for MSM8974 and DB8074 board
  ARM: dts: MSM8974: Add pinctrl node

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2014-05-23 23:30:17 +02:00
parent 77579afc35 08f9234ad6
commit 4078679ecf
4 changed files with 168 additions and 0 deletions
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13
arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
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@@ -3,4 +3,17 @@
/ {
model = "Qualcomm APQ8074 Dragonboard";
compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
soc: soc {
sdhci@f9824900 {
bus-width = <8>;
non-removable;
status = "ok";
};
sdhci@f98a4900 {
cd-gpios = <&msmgpio 62 0x1>;
bus-width = <4>;
};
};
};

51
arch/arm/boot/dts/qcom-msm8974.dtsi
View File

@@ -192,11 +192,62 @@
clock-names = "core", "iface";
};
sdhci@f9824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <0 123 0>, <0 138 0>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
sdhci@f98a4900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
rng@f9bff000 {
compatible = "qcom,prng";
reg = <0xf9bff000 0x200>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
msmgpio: pinctrl@fd510000 {
compatible = "qcom,msm8974-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
spi8_default: spi8_default {
mosi {
pins = "gpio45";
function = "blsp_spi8";
};
miso {
pins = "gpio46";
function = "blsp_spi8";
};
cs {
pins = "gpio47";
function = "blsp_spi8";
};
clk {
pins = "gpio48";
function = "blsp_spi8";
};
};
};
};
};