x86/fpu: Rename xsave.header::xstate_bv to 'xfeatures'
'xsave.header::xstate_bv' is a misnomer - what does 'bv' stand for? It probably comes from the 'XGETBV' instruction name, but I could not find in the Intel documentation where that abbreviation comes from. It could mean 'bit vector' - or something else? But how about - instead of guessing about a weird name - we named the field in an obvious and descriptive way that tells us exactly what it does? So rename it to 'xfeatures', which is a bitmask of the xfeatures that are fpstate_active in that context structure. Eyesore like: fpu->state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP; is now much more readable: fpu->state->xsave.header.xfeatures |= XSTATE_FP; Which form is not just infinitely more readable, but is also shorter as well. Reviewed-by: Borislav Petkov <bp@alien8.de> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@@ -470,7 +470,7 @@ int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
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* presence of FP and SSE state.
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*/
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if (cpu_has_xsave)
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fpu->state->xsave.header.xstate_bv |= XSTATE_FPSSE;
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fpu->state->xsave.header.xfeatures |= XSTATE_FPSSE;
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return ret;
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}
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@@ -528,7 +528,7 @@ int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
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* mxcsr reserved bits must be masked to zero for security reasons.
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*/
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xsave->i387.mxcsr &= mxcsr_feature_mask;
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xsave->header.xstate_bv &= xfeatures_mask;
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xsave->header.xfeatures &= xfeatures_mask;
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/*
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* These bits must be zero.
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*/
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@@ -740,7 +740,7 @@ int fpregs_set(struct task_struct *target, const struct user_regset *regset,
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* presence of FP.
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*/
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if (cpu_has_xsave)
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fpu->state->xsave.header.xstate_bv |= XSTATE_FP;
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fpu->state->xsave.header.xfeatures |= XSTATE_FP;
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return ret;
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}
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@@ -32,7 +32,7 @@ static unsigned int xfeatures_nr;
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/*
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* If a processor implementation discern that a processor state component is
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* in its initialized state it may modify the corresponding bit in the
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* header.xstate_bv as '0', with out modifying the corresponding memory
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* header.xfeatures as '0', with out modifying the corresponding memory
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* layout in the case of xsaveopt. While presenting the xstate information to
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* the user, we always ensure that the memory layout of a feature will be in
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* the init state if the corresponding header bit is zero. This is to ensure
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@@ -43,24 +43,24 @@ void __sanitize_i387_state(struct task_struct *tsk)
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{
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struct i387_fxsave_struct *fx = &tsk->thread.fpu.state->fxsave;
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int feature_bit = 0x2;
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u64 xstate_bv;
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u64 xfeatures;
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if (!fx)
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return;
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xstate_bv = tsk->thread.fpu.state->xsave.header.xstate_bv;
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xfeatures = tsk->thread.fpu.state->xsave.header.xfeatures;
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/*
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* None of the feature bits are in init state. So nothing else
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* to do for us, as the memory layout is up to date.
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*/
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if ((xstate_bv & xfeatures_mask) == xfeatures_mask)
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if ((xfeatures & xfeatures_mask) == xfeatures_mask)
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return;
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/*
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* FP is in init state
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*/
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if (!(xstate_bv & XSTATE_FP)) {
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if (!(xfeatures & XSTATE_FP)) {
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fx->cwd = 0x37f;
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fx->swd = 0;
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fx->twd = 0;
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@@ -73,17 +73,17 @@ void __sanitize_i387_state(struct task_struct *tsk)
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/*
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* SSE is in init state
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*/
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if (!(xstate_bv & XSTATE_SSE))
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if (!(xfeatures & XSTATE_SSE))
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memset(&fx->xmm_space[0], 0, 256);
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xstate_bv = (xfeatures_mask & ~xstate_bv) >> 2;
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xfeatures = (xfeatures_mask & ~xfeatures) >> 2;
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/*
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* Update all the other memory layouts for which the corresponding
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* header bit is in the init state.
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*/
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while (xstate_bv) {
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if (xstate_bv & 0x1) {
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while (xfeatures) {
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if (xfeatures & 0x1) {
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int offset = xstate_offsets[feature_bit];
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int size = xstate_sizes[feature_bit];
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@@ -92,7 +92,7 @@ void __sanitize_i387_state(struct task_struct *tsk)
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size);
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}
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xstate_bv >>= 1;
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xfeatures >>= 1;
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feature_bit++;
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}
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}
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@@ -162,7 +162,7 @@ static inline int save_xstate_epilog(void __user *buf, int ia32_frame)
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{
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struct xsave_struct __user *x = buf;
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struct _fpx_sw_bytes *sw_bytes;
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u32 xstate_bv;
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u32 xfeatures;
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int err;
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/* Setup the bytes not touched by the [f]xsave and reserved for SW. */
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@@ -175,25 +175,25 @@ static inline int save_xstate_epilog(void __user *buf, int ia32_frame)
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err |= __put_user(FP_XSTATE_MAGIC2, (__u32 *)(buf + xstate_size));
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/*
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* Read the xstate_bv which we copied (directly from the cpu or
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* Read the xfeatures which we copied (directly from the cpu or
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* from the state in task struct) to the user buffers.
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*/
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err |= __get_user(xstate_bv, (__u32 *)&x->header.xstate_bv);
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err |= __get_user(xfeatures, (__u32 *)&x->header.xfeatures);
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/*
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* For legacy compatible, we always set FP/SSE bits in the bit
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* vector while saving the state to the user context. This will
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* enable us capturing any changes(during sigreturn) to
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* the FP/SSE bits by the legacy applications which don't touch
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* xstate_bv in the xsave header.
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* xfeatures in the xsave header.
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*
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* xsave aware apps can change the xstate_bv in the xsave
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* xsave aware apps can change the xfeatures in the xsave
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* header as well as change any contents in the memory layout.
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* xrestore as part of sigreturn will capture all the changes.
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*/
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xstate_bv |= XSTATE_FPSSE;
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xfeatures |= XSTATE_FPSSE;
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err |= __put_user(xstate_bv, (__u32 *)&x->header.xstate_bv);
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err |= __put_user(xfeatures, (__u32 *)&x->header.xfeatures);
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return err;
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}
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@@ -277,7 +277,7 @@ int save_xstate_sig(void __user *buf, void __user *buf_fx, int size)
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static inline void
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sanitize_restored_xstate(struct task_struct *tsk,
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struct user_i387_ia32_struct *ia32_env,
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u64 xstate_bv, int fx_only)
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u64 xfeatures, int fx_only)
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{
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struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave;
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struct xstate_header *header = &xsave->header;
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@@ -291,9 +291,9 @@ sanitize_restored_xstate(struct task_struct *tsk,
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* layout and not enabled by the OS.
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*/
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if (fx_only)
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header->xstate_bv = XSTATE_FPSSE;
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header->xfeatures = XSTATE_FPSSE;
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else
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header->xstate_bv &= (xfeatures_mask & xstate_bv);
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header->xfeatures &= (xfeatures_mask & xfeatures);
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}
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if (use_fxsr()) {
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@@ -335,7 +335,7 @@ int __restore_xstate_sig(void __user *buf, void __user *buf_fx, int size)
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struct task_struct *tsk = current;
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struct fpu *fpu = &tsk->thread.fpu;
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int state_size = xstate_size;
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u64 xstate_bv = 0;
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u64 xfeatures = 0;
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int fx_only = 0;
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ia32_fxstate &= (config_enabled(CONFIG_X86_32) ||
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@@ -369,7 +369,7 @@ int __restore_xstate_sig(void __user *buf, void __user *buf_fx, int size)
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fx_only = 1;
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} else {
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state_size = fx_sw_user.xstate_size;
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xstate_bv = fx_sw_user.xstate_bv;
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xfeatures = fx_sw_user.xfeatures;
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}
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}
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@@ -398,7 +398,7 @@ int __restore_xstate_sig(void __user *buf, void __user *buf_fx, int size)
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fpstate_init(fpu);
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err = -1;
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} else {
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sanitize_restored_xstate(tsk, &env, xstate_bv, fx_only);
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sanitize_restored_xstate(tsk, &env, xfeatures, fx_only);
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}
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fpu->fpstate_active = 1;
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@@ -415,7 +415,7 @@ int __restore_xstate_sig(void __user *buf, void __user *buf_fx, int size)
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* state to the registers directly (with exceptions handled).
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*/
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user_fpu_begin();
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if (restore_user_xstate(buf_fx, xstate_bv, fx_only)) {
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if (restore_user_xstate(buf_fx, xfeatures, fx_only)) {
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fpu_reset_state(fpu);
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return -1;
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}
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@@ -441,7 +441,7 @@ static void prepare_fx_sw_frame(void)
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fx_sw_reserved.magic1 = FP_XSTATE_MAGIC1;
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fx_sw_reserved.extended_size = size;
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fx_sw_reserved.xstate_bv = xfeatures_mask;
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fx_sw_reserved.xfeatures = xfeatures_mask;
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fx_sw_reserved.xstate_size = xstate_size;
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if (config_enabled(CONFIG_IA32_EMULATION)) {
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@@ -576,7 +576,7 @@ static void __init setup_init_fpu_buf(void)
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if (cpu_has_xsaves) {
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init_xstate_buf->header.xcomp_bv =
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(u64)1 << 63 | xfeatures_mask;
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init_xstate_buf->header.xstate_bv = xfeatures_mask;
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init_xstate_buf->header.xfeatures = xfeatures_mask;
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}
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/*
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