Merge branches 'ib-mfd-arm-i2c-4.14', 'ib-mfd-arm-usb-video-4.14', 'ib-mfd-hwmon-4.14', 'ib-mfd-iio-pwm-4.14', 'ib-mfd-input-rtc-4.14', 'ib-mfd-many-4.14' and 'ib-mfd-pinctrl-regulator-4.14' into ibs-for-mfd-merged
This commit is contained in:
@@ -75,7 +75,7 @@
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pinctrl-names = "default";
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pinctrl-0 = <&pca0_pins>;
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interrupt-parent = <&gpio0>;
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interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
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interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@@ -87,7 +87,7 @@
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compatible = "nxp,pca9555";
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pinctrl-names = "default";
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interrupt-parent = <&gpio0>;
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interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
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interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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@@ -301,25 +301,4 @@
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pinctrl-names = "default";
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pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
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status = "okay";
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/* VPIF capture port */
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port@0 {
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vpif_input_ch0: endpoint@0 {
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reg = <0>;
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bus-width = <8>;
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};
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vpif_input_ch1: endpoint@1 {
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reg = <1>;
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bus-width = <8>;
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data-shift = <8>;
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};
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};
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/* VPIF display port */
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port@1 {
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vpif_output_ch0: endpoint {
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bus-width = <8>;
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};
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};
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};
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@@ -318,11 +318,4 @@
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pinctrl-names = "default";
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pinctrl-0 = <&vpif_capture_pins>;
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status = "okay";
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/* VPIF capture port */
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port {
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vpif_ch0: endpoint {
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bus-width = <8>;
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};
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};
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};
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@@ -68,6 +68,34 @@
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DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */
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>;
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};
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nandflash_pins: nandflash_pins {
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pinctrl-single,pins = <
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DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0) /* PINCTRL207 GPMC_CS0*/
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DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0) /* PINCTRL217 GPMC_ADV_ALE */
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DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0) /* PINCTRL214 GPMC_OE_RE */
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DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0) /* PINCTRL215 GPMC_BE0_CLE */
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DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0) /* PINCTRL213 GPMC_WE */
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DM816X_IOPAD(0x0b6c, MUX_MODE0) /* PINCTRL220 GPMC_WAIT */
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DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0) /* PINCTRL250 GPMC_CLK */
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DM816X_IOPAD(0x0ba4, MUX_MODE0) /* PINCTRL234 GPMC_D0 */
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DM816X_IOPAD(0x0ba8, MUX_MODE0) /* PINCTRL234 GPMC_D1 */
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DM816X_IOPAD(0x0bac, MUX_MODE0) /* PINCTRL234 GPMC_D2 */
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DM816X_IOPAD(0x0bb0, MUX_MODE0) /* PINCTRL234 GPMC_D3 */
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DM816X_IOPAD(0x0bb4, MUX_MODE0) /* PINCTRL234 GPMC_D4 */
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DM816X_IOPAD(0x0bb8, MUX_MODE0) /* PINCTRL234 GPMC_D5 */
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DM816X_IOPAD(0x0bbc, MUX_MODE0) /* PINCTRL234 GPMC_D6 */
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DM816X_IOPAD(0x0bc0, MUX_MODE0) /* PINCTRL234 GPMC_D7 */
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DM816X_IOPAD(0x0bc4, MUX_MODE0) /* PINCTRL234 GPMC_D8 */
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DM816X_IOPAD(0x0bc8, MUX_MODE0) /* PINCTRL234 GPMC_D9 */
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DM816X_IOPAD(0x0bcc, MUX_MODE0) /* PINCTRL234 GPMC_D10 */
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DM816X_IOPAD(0x0bd0, MUX_MODE0) /* PINCTRL234 GPMC_D11 */
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DM816X_IOPAD(0x0bd4, MUX_MODE0) /* PINCTRL234 GPMC_D12 */
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DM816X_IOPAD(0x0bd8, MUX_MODE0) /* PINCTRL234 GPMC_D13 */
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DM816X_IOPAD(0x0bdc, MUX_MODE0) /* PINCTRL234 GPMC_D14 */
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DM816X_IOPAD(0x0be0, MUX_MODE0) /* PINCTRL234 GPMC_D15 */
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>;
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};
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};
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&i2c1 {
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@@ -90,6 +118,8 @@
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&gpmc {
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ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
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pinctrl-names = "default";
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pinctrl-0 = <&nandflash_pins>;
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nand@0,0 {
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compatible = "ti,omap2-nand";
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@@ -98,9 +128,11 @@
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
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#address-cells = <1>;
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#size-cells = <1>;
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <16>;
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gpmc,device-width = <2>;
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gpmc,sync-clk-ps = <0>;
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@@ -164,7 +196,7 @@
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vmmc-supply = <&vmmcsd_fixed>;
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bus-width = <4>;
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cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
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};
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/* At least dm8168-evm rev c won't support multipoint, later may */
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@@ -145,7 +145,7 @@
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};
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elm: elm@48080000 {
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compatible = "ti,816-elm";
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compatible = "ti,am3352-elm";
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ti,hwmods = "elm";
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reg = <0x48080000 0x2000>;
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interrupts = <4>;
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@@ -190,7 +190,7 @@
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
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ti,impedance-control = <0x1f>;
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ti,min-output-impedance;
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};
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dp83867_1: ethernet-phy@3 {
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@@ -198,7 +198,7 @@
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
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ti,impedance-control = <0x1f>;
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ti,min-output-impedance;
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};
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};
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@@ -59,6 +59,9 @@
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compatible = "samsung,exynos4210-audss-clock";
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reg = <0x03810000 0x0C>;
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#clock-cells = <1>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
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<&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;
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clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
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};
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i2s0: i2s@03830000 {
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@@ -266,6 +266,7 @@
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&hdmicec {
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status = "okay";
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needs-hpd;
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};
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&hsi2c_4 {
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@@ -297,6 +297,7 @@
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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ranges;
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adc: adc@50030800 {
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compatible = "fsl,imx25-gcq";
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@@ -507,7 +507,7 @@
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pinctrl_pcie: pciegrp {
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fsl,pins = <
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/* PCIe reset */
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MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x030b0
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MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x030b0
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MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x030b0
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>;
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};
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@@ -668,7 +668,7 @@
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&pcie {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie>;
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reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>;
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reset-gpio = <&gpio3 0 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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@@ -557,6 +557,14 @@
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>;
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};
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pinctrl_spi4: spi4grp {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
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MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
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MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
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>;
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};
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pinctrl_tsc2046_pendown: tsc2046_pendown {
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fsl,pins = <
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MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59
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@@ -697,13 +705,5 @@
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fsl,pins = <
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MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x110b0
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>;
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pinctrl_spi4: spi4grp {
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fsl,pins = <
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MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59
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MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
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MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
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>;
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};
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};
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};
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@@ -1126,8 +1126,8 @@
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};
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};
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gpu: mali@ffa30000 {
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compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
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gpu: gpu@ffa30000 {
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compatible = "rockchip,rk3288-mali", "arm,mali-t760";
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reg = <0xffa30000 0x10000>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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@@ -303,7 +303,7 @@
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#size-cells = <1>;
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atmel,smc = <&hsmc>;
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reg = <0x10000000 0x10000000
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0x40000000 0x30000000>;
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0x60000000 0x30000000>;
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ranges = <0x0 0x0 0x10000000 0x10000000
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0x1 0x0 0x60000000 0x10000000
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0x2 0x0 0x70000000 0x10000000
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@@ -1048,18 +1048,18 @@
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};
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hsmc: hsmc@f8014000 {
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compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
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compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
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reg = <0xf8014000 0x1000>;
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
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clocks = <&hsmc_clk>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pmecc: ecc-engine@ffffc070 {
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pmecc: ecc-engine@f8014070 {
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compatible = "atmel,sama5d2-pmecc";
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reg = <0xffffc070 0x490>,
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<0xffffc500 0x100>;
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reg = <0xf8014070 0x490>,
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<0xf8014500 0x100>;
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};
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};
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|
@@ -44,7 +44,9 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun8i-a83t-ccu.h>
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#include <dt-bindings/clock/sun8i-r-ccu.h>
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#include <dt-bindings/reset/sun8i-a83t-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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@@ -175,8 +177,8 @@
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compatible = "allwinner,sun8i-a83t-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu 21>;
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resets = <&ccu 7>;
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clocks = <&ccu CLK_BUS_DMA>;
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resets = <&ccu RST_BUS_DMA>;
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#dma-cells = <1>;
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};
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@@ -195,7 +197,7 @@
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x01c20800 0x400>;
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clocks = <&ccu 45>, <&osc24M>, <&osc16Md512>;
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clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
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clock-names = "apb", "hosc", "losc";
|
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gpio-controller;
|
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interrupt-controller;
|
||||
@@ -247,8 +249,8 @@
|
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"allwinner,sun8i-h3-spdif";
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reg = <0x01c21000 0x400>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu 44>, <&ccu 76>;
|
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resets = <&ccu 32>;
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clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
|
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resets = <&ccu RST_BUS_SPDIF>;
|
||||
clock-names = "apb", "spdif";
|
||||
dmas = <&dma 2>;
|
||||
dma-names = "tx";
|
||||
@@ -263,8 +265,8 @@
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&ccu 53>;
|
||||
resets = <&ccu 40>;
|
||||
clocks = <&ccu CLK_BUS_UART0>;
|
||||
resets = <&ccu RST_BUS_UART0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@@ -56,8 +56,6 @@
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
|
||||
ethernet0 = &emac;
|
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ethernet1 = &xr819;
|
||||
};
|
||||
|
||||
@@ -104,13 +102,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emac {
|
||||
phy-handle = <&int_mii_phy>;
|
||||
phy-mode = "mii";
|
||||
allwinner,leds-active-low;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc0_pins_a>;
|
||||
|
@@ -52,7 +52,6 @@
|
||||
compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &emac;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
@@ -115,30 +114,12 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emac_rgmii_pins>;
|
||||
phy-supply = <®_gmac_3v3>;
|
||||
phy-handle = <&ext_rgmii_phy>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
allwinner,leds-active-low;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ir {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ir_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
ext_rgmii_phy: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
|
||||
|
@@ -46,10 +46,3 @@
|
||||
model = "FriendlyARM NanoPi NEO";
|
||||
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
|
||||
};
|
||||
|
||||
&emac {
|
||||
phy-handle = <&int_mii_phy>;
|
||||
phy-mode = "mii";
|
||||
allwinner,leds-active-low;
|
||||
status = "okay";
|
||||
};
|
||||
|
@@ -54,7 +54,6 @@
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
|
||||
ethernet0 = &emac;
|
||||
ethernet1 = &rtl8189;
|
||||
};
|
||||
|
||||
@@ -118,13 +117,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emac {
|
||||
phy-handle = <&int_mii_phy>;
|
||||
phy-mode = "mii";
|
||||
allwinner,leds-active-low;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ir {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ir_pins_a>;
|
||||
|
@@ -52,7 +52,6 @@
|
||||
compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &emac;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
@@ -98,13 +97,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emac {
|
||||
phy-handle = <&int_mii_phy>;
|
||||
phy-mode = "mii";
|
||||
allwinner,leds-active-low;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
|
||||
|
@@ -53,11 +53,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
&emac {
|
||||
/* LEDs changed to active high on the plus */
|
||||
/delete-property/ allwinner,leds-active-low;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins_a>;
|
||||
|
@@ -52,7 +52,6 @@
|
||||
compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &emac;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
@@ -114,13 +113,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emac {
|
||||
phy-handle = <&int_mii_phy>;
|
||||
phy-mode = "mii";
|
||||
allwinner,leds-active-low;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ir {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ir_pins_a>;
|
||||
|
@@ -47,10 +47,6 @@
|
||||
model = "Xunlong Orange Pi Plus / Plus 2";
|
||||
compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &emac;
|
||||
};
|
||||
|
||||
reg_gmac_3v3: gmac-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "gmac-3v3";
|
||||
@@ -78,24 +74,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emac_rgmii_pins>;
|
||||
phy-supply = <®_gmac_3v3>;
|
||||
phy-handle = <&ext_rgmii_phy>;
|
||||
phy-mode = "rgmii";
|
||||
|
||||
allwinner,leds-active-low;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
ext_rgmii_phy: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_8bit_pins>;
|
||||
|
@@ -61,19 +61,3 @@
|
||||
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
|
||||
};
|
||||
};
|
||||
|
||||
&emac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emac_rgmii_pins>;
|
||||
phy-supply = <®_gmac_3v3>;
|
||||
phy-handle = <&ext_rgmii_phy>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
||||
ext_rgmii_phy: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
@@ -391,32 +391,6 @@
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
emac: ethernet@1c30000 {
|
||||
compatible = "allwinner,sun8i-h3-emac";
|
||||
syscon = <&syscon>;
|
||||
reg = <0x01c30000 0x104>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
resets = <&ccu RST_BUS_EMAC>;
|
||||
reset-names = "stmmaceth";
|
||||
clocks = <&ccu CLK_BUS_EMAC>;
|
||||
clock-names = "stmmaceth";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
int_mii_phy: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
clocks = <&ccu CLK_BUS_EPHY>;
|
||||
resets = <&ccu RST_BUS_EPHY>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@01c68000 {
|
||||
compatible = "allwinner,sun8i-h3-spi";
|
||||
reg = <0x01c68000 0x1000>;
|
||||
|
@@ -22,7 +22,7 @@
|
||||
};
|
||||
|
||||
ð0 {
|
||||
phy-connection-type = "rgmii";
|
||||
phy-connection-type = "rgmii-id";
|
||||
phy-handle = <ð0_phy>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
Reference in New Issue
Block a user