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Merge branches 'clk-optional', 'clk-devm-clkdev-register', 'clk-allwinner', 'clk-meson' and 'clk-renesas' into clk-next

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- Add a {devm_}clk_get_optional() API
 - Add devm_clk_hw_register_clkdev() API to manage clkdev lookups

* clk-optional:
  clk: Add (devm_)clk_get_optional() functions
  clk: Add comment about __of_clk_get_by_name() error values

* clk-devm-clkdev-register:
  clk: clk-st: avoid clkdev lookup leak at remove
  clk: clk-max77686: Clean clkdev lookup leak and use devm
  clkdev: add managed clkdev lookup registration

* clk-allwinner:
  clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating it

* clk-meson: (22 commits)
  clk: meson: meson8b: fix the naming of the APB clocks
  dt-bindings: clock: meson8b: add APB clock definition
  clk: meson: Add G12A AO Clock + Reset Controller
  dt-bindings: clk: add G12A AO Clock and Reset Bindings
  clk: meson: factorise meson64 peripheral clock controller drivers
  clk: meson: g12a: add peripheral clock controller
  dt-bindings: clk: meson: add g12a periph clock controller bindings
  clk: meson: pll: update driver for the g12a
  clk: meson: rework and clean drivers dependencies
  clk: meson: axg-audio does not require syscon
  clk: meson: use CONFIG_ARCH_MESON to enter meson clk directory
  clk: export some clk_hw function symbols for module drivers
  clk: meson: ao-clkc: claim clock controller input clocks from DT
  clk: meson: axg: claim clock controller input clock from DT
  clk: meson: gxbb: claim clock controller input clock from DT
  clk: meson: meson8b: add the GPU clock tree
  clk: meson: meson8b: use a separate clock table for Meson8
  clk: meson: axg-ao: add 32k generation subtree
  clk: meson: gxbb-ao: replace cec-32k with the dual divider
  clk: meson: add dual divider clock driver
  ...

* clk-renesas:
  clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLK
  clk: renesas: r8a774c0: Fix LAST_DT_CORE_CLK
  clk: renesas: r8a774c0: Add TMU clock
  clk: renesas: r8a77980: Add RPC clocks
  clk: renesas: rcar-gen3: Add RPC clocks
  clk: renesas: rcar-gen3: Add spinlock
  clk: renesas: rcar-gen3: Factor out cpg_reg_modify()
  clk: renesas: r8a774c0: Correct parent clock of DU
  clk: renesas: r8a774a1: Add missing CANFD clock
  clk: renesas: r8a774c0: Add missing CANFD clock
This commit is contained in:
Stephen Boyd
2019-03-08 10:27:21 -08:00
parent 7e2570031a 60b8f0ddf1 d3236214e7 da392a5ab4 a9ca321716 df446f7e6e
commit 3f8e7e7247
64 changed files with 5450 additions and 834 deletions
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7
include/dt-bindings/clock/axg-aoclkc.h
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@@ -21,6 +21,11 @@
#define CLKID_AO_SAR_ADC_SEL 8
#define CLKID_AO_SAR_ADC_DIV 9
#define CLKID_AO_SAR_ADC_CLK 10
#define CLKID_AO_ALT_XTAL 11
#define CLKID_AO_CTS_OSCIN 11
#define CLKID_AO_32K_PRE 12
#define CLKID_AO_32K_DIV 13
#define CLKID_AO_32K_SEL 14
#define CLKID_AO_32K 15
#define CLKID_AO_CTS_RTC_OSCIN 16
#endif

34
include/dt-bindings/clock/g12a-aoclkc.h Normal file
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@@ -0,0 +1,34 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
/*
* Copyright (c) 2016 BayLibre, SAS
* Author: Neil Armstrong <narmstrong@baylibre.com>
*
* Copyright (c) 2018 Amlogic, inc.
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
*/
#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
#define CLKID_AO_AHB 0
#define CLKID_AO_IR_IN 1
#define CLKID_AO_I2C_M0 2
#define CLKID_AO_I2C_S0 3
#define CLKID_AO_UART 4
#define CLKID_AO_PROD_I2C 5
#define CLKID_AO_UART2 6
#define CLKID_AO_IR_OUT 7
#define CLKID_AO_SAR_ADC 8
#define CLKID_AO_MAILBOX 9
#define CLKID_AO_M3 10
#define CLKID_AO_AHB_SRAM 11
#define CLKID_AO_RTI 12
#define CLKID_AO_M4_FCLK 13
#define CLKID_AO_M4_HCLK 14
#define CLKID_AO_CLK81 15
#define CLKID_AO_SAR_ADC_CLK 18
#define CLKID_AO_32K 23
#define CLKID_AO_CEC 27
#define CLKID_AO_CTS_RTC_OSCIN 28
#endif

135
include/dt-bindings/clock/g12a-clkc.h Normal file
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@@ -0,0 +1,135 @@
/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
/*
* Meson-G12A clock tree IDs
*
* Copyright (c) 2018 Amlogic, Inc. All rights reserved.
*/
#ifndef __G12A_CLKC_H
#define __G12A_CLKC_H
#define CLKID_SYS_PLL 0
#define CLKID_FIXED_PLL 1
#define CLKID_FCLK_DIV2 2
#define CLKID_FCLK_DIV3 3
#define CLKID_FCLK_DIV4 4
#define CLKID_FCLK_DIV5 5
#define CLKID_FCLK_DIV7 6
#define CLKID_GP0_PLL 7
#define CLKID_CLK81 10
#define CLKID_MPLL0 11
#define CLKID_MPLL1 12
#define CLKID_MPLL2 13
#define CLKID_MPLL3 14
#define CLKID_DDR 15
#define CLKID_DOS 16
#define CLKID_AUDIO_LOCKER 17
#define CLKID_MIPI_DSI_HOST 18
#define CLKID_ETH_PHY 19
#define CLKID_ISA 20
#define CLKID_PL301 21
#define CLKID_PERIPHS 22
#define CLKID_SPICC0 23
#define CLKID_I2C 24
#define CLKID_SANA 25
#define CLKID_SD 26
#define CLKID_RNG0 27
#define CLKID_UART0 28
#define CLKID_SPICC1 29
#define CLKID_HIU_IFACE 30
#define CLKID_MIPI_DSI_PHY 31
#define CLKID_ASSIST_MISC 32
#define CLKID_SD_EMMC_A 33
#define CLKID_SD_EMMC_B 34
#define CLKID_SD_EMMC_C 35
#define CLKID_AUDIO_CODEC 36
#define CLKID_AUDIO 37
#define CLKID_ETH 38
#define CLKID_DEMUX 39
#define CLKID_AUDIO_IFIFO 40
#define CLKID_ADC 41
#define CLKID_UART1 42
#define CLKID_G2D 43
#define CLKID_RESET 44
#define CLKID_PCIE_COMB 45
#define CLKID_PARSER 46
#define CLKID_USB 47
#define CLKID_PCIE_PHY 48
#define CLKID_AHB_ARB0 49
#define CLKID_AHB_DATA_BUS 50
#define CLKID_AHB_CTRL_BUS 51
#define CLKID_HTX_HDCP22 52
#define CLKID_HTX_PCLK 53
#define CLKID_BT656 54
#define CLKID_USB1_DDR_BRIDGE 55
#define CLKID_MMC_PCLK 56
#define CLKID_UART2 57
#define CLKID_VPU_INTR 58
#define CLKID_GIC 59
#define CLKID_SD_EMMC_A_CLK0 60
#define CLKID_SD_EMMC_B_CLK0 61
#define CLKID_SD_EMMC_C_CLK0 62
#define CLKID_HIFI_PLL 74
#define CLKID_VCLK2_VENCI0 80
#define CLKID_VCLK2_VENCI1 81
#define CLKID_VCLK2_VENCP0 82
#define CLKID_VCLK2_VENCP1 83
#define CLKID_VCLK2_VENCT0 84
#define CLKID_VCLK2_VENCT1 85
#define CLKID_VCLK2_OTHER 86
#define CLKID_VCLK2_ENCI 87
#define CLKID_VCLK2_ENCP 88
#define CLKID_DAC_CLK 89
#define CLKID_AOCLK 90
#define CLKID_IEC958 91
#define CLKID_ENC480P 92
#define CLKID_RNG1 93
#define CLKID_VCLK2_ENCT 94
#define CLKID_VCLK2_ENCL 95
#define CLKID_VCLK2_VENCLMMC 96
#define CLKID_VCLK2_VENCL 97
#define CLKID_VCLK2_OTHER1 98
#define CLKID_FCLK_DIV2P5 99
#define CLKID_DMA 105
#define CLKID_EFUSE 106
#define CLKID_ROM_BOOT 107
#define CLKID_RESET_SEC 108
#define CLKID_SEC_AHB_APB3 109
#define CLKID_VPU_0_SEL 110
#define CLKID_VPU_0 112
#define CLKID_VPU_1_SEL 113
#define CLKID_VPU_1 115
#define CLKID_VPU 116
#define CLKID_VAPB_0_SEL 117
#define CLKID_VAPB_0 119
#define CLKID_VAPB_1_SEL 120
#define CLKID_VAPB_1 122
#define CLKID_VAPB_SEL 123
#define CLKID_VAPB 124
#define CLKID_HDMI_PLL 128
#define CLKID_VID_PLL 129
#define CLKID_VCLK 138
#define CLKID_VCLK2 139
#define CLKID_VCLK_DIV1 148
#define CLKID_VCLK_DIV2 149
#define CLKID_VCLK_DIV4 150
#define CLKID_VCLK_DIV6 151
#define CLKID_VCLK_DIV12 152
#define CLKID_VCLK2_DIV1 153
#define CLKID_VCLK2_DIV2 154
#define CLKID_VCLK2_DIV4 155
#define CLKID_VCLK2_DIV6 156
#define CLKID_VCLK2_DIV12 157
#define CLKID_CTS_ENCI 162
#define CLKID_CTS_ENCP 163
#define CLKID_CTS_VDAC 164
#define CLKID_HDMI_TX 165
#define CLKID_HDMI 168
#define CLKID_MALI_0_SEL 169
#define CLKID_MALI_0 171
#define CLKID_MALI_1_SEL 172
#define CLKID_MALI_1 174
#define CLKID_MALI 175
#define CLKID_MPLL_5OM 177
#endif /* __G12A_CLKC_H */

7
include/dt-bindings/clock/gxbb-aoclkc.h
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@@ -63,5 +63,12 @@
#define CLKID_AO_UART2 4
#define CLKID_AO_IR_BLASTER 5
#define CLKID_AO_CEC_32K 6
#define CLKID_AO_CTS_OSCIN 7
#define CLKID_AO_32K_PRE 8
#define CLKID_AO_32K_DIV 9
#define CLKID_AO_32K_SEL 10
#define CLKID_AO_32K 11
#define CLKID_AO_CTS_RTC_OSCIN 12
#define CLKID_AO_CLK81 13
#endif

1
include/dt-bindings/clock/meson8b-clkc.h
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@@ -104,6 +104,7 @@
#define CLKID_MPLL2 95
#define CLKID_NAND_CLK 112
#define CLKID_ABP 124
#define CLKID_APB 124
#define CLKID_PERIPH 126
#define CLKID_AXI 128
#define CLKID_L2_DRAM 130

1
include/dt-bindings/clock/r8a774a1-cpg-mssr.h
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@@ -54,5 +54,6 @@
#define R8A774A1_CLK_CPEX 43
#define R8A774A1_CLK_R 44
#define R8A774A1_CLK_OSC 45
#define R8A774A1_CLK_CANFD 46
#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */

1
include/dt-bindings/clock/r8a774c0-cpg-mssr.h
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@@ -56,5 +56,6 @@
#define R8A774C0_CLK_CSI0 45
#define R8A774C0_CLK_CP 46
#define R8A774C0_CLK_CPEX 47
#define R8A774C0_CLK_CANFD 48
#endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */