Merge branch 'lorenzo/pci/tegra'
- Fix Tegra OF node reference leak (Nishka Dasgupta)
- Add #defines for PCIe Data Link Feature and Physical Layer 16.0 GT/s
features (Vidya Sagar)
- Disable MSI for Tegra Root Ports since they don't support using MSI for
all Root Port events (Vidya Sagar)
- Group DesignWare write-protected register writes together (Vidya Sagar)
- Move DesignWare capability search interfaces so they can be used by
both host and endpoint drivers (Vidya Sagar)
- Add DesignWare extended capability search interfaces (Vidya Sagar)
- Export dw_pcie_wait_for_link() so drivers can be modules (Vidya Sagar)
- Add "snps,enable-cdm-check" DT binding for Configuration Dependent
Module (CDM) register checking (Vidya Sagar)
- Add DesignWare support for "snps,enable-cdm-check" CDM checking (Vidya
Sagar)
- Add "supports-clkreq" DT binding for host drivers to decide whether to
advertise low power features (Vidya Sagar)
- Add DT binding for Tegra194 (Vidya Sagar)
- Add DT binding for Tegra194 P2U (PIPE to UPHY) block (Vidya Sagar)
- Add support for Tegra194 P2U (PIPE to UPHY) (Vidya Sagar)
- Add support for Tegra194 host controller (Vidya Sagar)
- Add Tegra support for sideband PERST# and CLKREQ# for C5 (Vidya Sagar)
- Add Tegra support for slot regulators for p2972-0000 platform (Vidya
Sagar)
* lorenzo/pci/tegra:
arm64: tegra: Add PCIe slot supply information in p2972-0000 platform
arm64: tegra: Add configuration for PCIe C5 sideband signals
PCI: tegra: Add support to enable slot regulators
PCI: tegra: Add support to configure sideband pins
dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries
dt-bindings: PCI: tegra: Add sideband pins configuration entries
PCI: tegra: Add Tegra194 PCIe support
phy: tegra: Add PCIe PIPE2UPHY support
dt-bindings: PHY: P2U: Add Tegra194 P2U block
dt-bindings: PCI: tegra: Add device tree support for Tegra194
dt-bindings: Add PCIe supports-clkreq property
PCI: dwc: Add support to enable CDM register check
dt-bindings: PCI: designware: Add binding for CDM register check
PCI: dwc: Export dw_pcie_wait_for_link() API
PCI: dwc: Add extended configuration space capability search API
PCI: dwc: Move config space capability search API
PCI: dwc: Group DBI registers writes requiring unlocking
PCI: Disable MSI for Tegra root ports
PCI: Add #defines for some of PCIe spec r4.0 features
PCI: tegra: Fix OF node reference leak
This commit is contained in:
Bjorn Helgaas
@@ -33,6 +33,11 @@ Optional properties:
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- clock-names: Must include the following entries:
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- "pcie"
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- "pcie_bus"
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- snps,enable-cdm-check: This is a boolean property and if present enables
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automatic checking of CDM (Configuration Dependent Module) registers
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for data corruption. CDM registers include standard PCIe configuration
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space registers, Port Logic registers, DMA and iATU (internal Address
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Translation Unit) registers.
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RC mode:
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- num-viewport: number of view ports configured in hardware. If a platform
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does not specify it, the driver assumes 2.
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171
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
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171
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
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@@ -0,0 +1,171 @@
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NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
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This PCIe host controller is based on the Synopsis Designware PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: For Tegra19x, must contain "nvidia,tegra194-pcie".
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- device_type: Must be "pci"
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- power-domains: A phandle to the node that controls power to the respective
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PCIe controller and a specifier name for the PCIe controller. Following are
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the specifiers for the different PCIe controllers
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TEGRA194_POWER_DOMAIN_PCIEX8B: C0
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TEGRA194_POWER_DOMAIN_PCIEX1A: C1
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TEGRA194_POWER_DOMAIN_PCIEX1A: C2
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TEGRA194_POWER_DOMAIN_PCIEX1A: C3
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TEGRA194_POWER_DOMAIN_PCIEX4A: C4
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TEGRA194_POWER_DOMAIN_PCIEX8A: C5
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these specifiers are defined in
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"include/dt-bindings/power/tegra194-powergate.h" file.
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- reg: A list of physical base address and length pairs for each set of
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controller registers. Must contain an entry for each entry in the reg-names
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property.
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- reg-names: Must include the following entries:
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"appl": Controller's application logic registers
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"config": As per the definition in designware-pcie.txt
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"atu_dma": iATU and DMA registers. This is where the iATU (internal Address
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Translation Unit) registers of the PCIe core are made available
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for SW access.
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"dbi": The aperture where root port's own configuration registers are
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available
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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"intr": The Tegra interrupt that is asserted for controller interrupts
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"msi": The Tegra interrupt that is asserted when an MSI is received
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- bus-range: Range of bus numbers associated with this controller
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- #address-cells: Address representation for root ports (must be 3)
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- cell 0 specifies the bus and device numbers of the root port:
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[23:16]: bus number
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[15:11]: device number
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- cell 1 denotes the upper 32 address bits and should be 0
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- cell 2 contains the lower 32 address bits and is used to translate to the
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CPU address space
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- #size-cells: Size representation for root ports (must be 2)
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- ranges: Describes the translation of addresses for root ports and standard
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PCI regions. The entries must be 7 cells each, where the first three cells
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correspond to the address as described for the #address-cells property
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above, the fourth and fifth cells are for the physical CPU address to
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translate to and the sixth and seventh cells are as described for the
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#size-cells property above.
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- Entries setup the mapping for the standard I/O, memory and
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prefetchable PCI regions. The first cell determines the type of region
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that is setup:
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- 0x81000000: I/O memory region
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- 0x82000000: non-prefetchable memory region
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- 0xc2000000: prefetchable memory region
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Please refer to the standard PCI bus binding document for a more detailed
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explanation.
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- #interrupt-cells: Size representation for interrupts (must be 1)
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- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
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Please refer to the standard PCI bus binding document for a more detailed
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explanation.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- core
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- apb
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- core
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- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
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- phy-names: Must include an entry for each active lane.
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"p2u-N": where N ranges from 0 to one less than the total number of lanes
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- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
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by controller-id. Following are the controller ids for each controller.
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0: C0
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1: C1
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2: C2
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3: C3
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4: C4
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5: C5
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- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
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Optional properties:
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- pinctrl-names: A list of pinctrl state names.
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It is mandatory for C5 controller and optional for other controllers.
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- "default": Configures PCIe I/O for proper operation.
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- pinctrl-0: phandle for the 'default' state of pin configuration.
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It is mandatory for C5 controller and optional for other controllers.
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- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
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- nvidia,update-fc-fixup: This is a boolean property and needs to be present to
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improve performance when a platform is designed in such a way that it
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satisfies at least one of the following conditions thereby enabling root
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port to exchange optimum number of FC (Flow Control) credits with
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downstream devices
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1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
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2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
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a) speed is Gen-2 and MPS is 256B
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b) speed is >= Gen-3 with any MPS
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- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
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to be specified in microseconds
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- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
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specified in microseconds
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- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
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specified in microseconds
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- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
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if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
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in p2972-0000 platform).
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- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
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if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
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in p2972-0000 platform).
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Examples:
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=========
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Tegra194:
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--------
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pcie@14180000 {
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compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
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reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
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0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
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0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
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reg-names = "appl", "config", "atu_dma";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <8>;
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linux,pci-domain = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
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clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
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clock-names = "core";
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resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
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<&bpmp TEGRA194_RESET_PEX0_CORE_0>;
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reset-names = "apb", "core";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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interrupt-names = "intr", "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,bpmp = <&bpmp 0>;
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supports-clkreq;
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nvidia,aspm-cmrt-us = <60>;
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nvidia,aspm-pwr-on-t-us = <20>;
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nvidia,aspm-l0s-entrance-latency-us = <3>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
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0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
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0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */
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vddio-pex-ctl-supply = <&vdd_1v8ao>;
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vpcie3v3-supply = <&vdd_3v3_pcie>;
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vpcie12v-supply = <&vdd_12v_pcie>;
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phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
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<&p2u_hsio_5>;
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phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
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};
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@@ -27,6 +27,11 @@ driver implementation may support the following properties:
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- reset-gpios:
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If present this property specifies PERST# GPIO. Host drivers can parse the
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GPIO and apply fundamental reset to endpoints.
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- supports-clkreq:
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If present this property specifies that CLKREQ signal routing exists from
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root port to downstream device and host bridge drivers can do programming
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which depends on CLKREQ signal existence. For example, programming root port
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not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
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PCI-PCI Bridge properties
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-------------------------
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28
Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
Normal file
28
Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
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@@ -0,0 +1,28 @@
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NVIDIA Tegra194 P2U binding
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Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
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Speed) each interfacing with 12 and 8 P2U instances respectively.
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A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
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interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
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lane.
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Required properties:
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- compatible: For Tegra19x, must contain "nvidia,tegra194-p2u".
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- reg: Should be the physical address space and length of respective each P2U
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instance.
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- reg-names: Must include the entry "ctl".
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Required properties for PHY port node:
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- #phy-cells: Defined by generic PHY bindings. Must be 0.
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Refer to phy/phy-bindings.txt for the generic PHY binding properties.
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Example:
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p2u_hsio_0: phy@3e10000 {
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compatible = "nvidia,tegra194-p2u";
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reg = <0x03e10000 0x10000>;
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reg-names = "ctl";
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#phy-cells = <0>;
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};
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