serial: 8250: Dissociate 4MHz Titan ports from Oxford ports
[ Upstream commit f771a34b141124a68265f91acae34cdb08aeb9e0 ] Oxford Semiconductor PCIe (Tornado) serial port devices have their baud base set incorrectly, however their `pciserial_board' entries have been reused for Titan serial port devices. Define own entries for the latter devices then, carrying over the settings, so that Oxford entries can be fixed. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Link: https://lore.kernel.org/r/alpine.DEB.2.21.2106100142310.5469@angie.orcam.me.uk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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committed by
Greg Kroah-Hartman

parent
85d6306a87
commit
3e9baedb32
@@ -2983,6 +2983,10 @@ enum pci_board_num_t {
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pbn_sunix_pci_4s,
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pbn_sunix_pci_4s,
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pbn_sunix_pci_8s,
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pbn_sunix_pci_8s,
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pbn_sunix_pci_16s,
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pbn_sunix_pci_16s,
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pbn_titan_1_4000000,
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pbn_titan_2_4000000,
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pbn_titan_4_4000000,
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pbn_titan_8_4000000,
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pbn_moxa8250_2p,
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pbn_moxa8250_2p,
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pbn_moxa8250_4p,
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pbn_moxa8250_4p,
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pbn_moxa8250_8p,
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pbn_moxa8250_8p,
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@@ -3770,6 +3774,34 @@ static struct pciserial_board pci_boards[] = {
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.base_baud = 921600,
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.base_baud = 921600,
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.uart_offset = 0x8,
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.uart_offset = 0x8,
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},
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},
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[pbn_titan_1_4000000] = {
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.flags = FL_BASE0,
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.num_ports = 1,
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.base_baud = 4000000,
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.uart_offset = 0x200,
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.first_offset = 0x1000,
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},
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[pbn_titan_2_4000000] = {
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.flags = FL_BASE0,
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.num_ports = 2,
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.base_baud = 4000000,
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.uart_offset = 0x200,
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.first_offset = 0x1000,
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},
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[pbn_titan_4_4000000] = {
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.flags = FL_BASE0,
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.num_ports = 4,
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.base_baud = 4000000,
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.uart_offset = 0x200,
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.first_offset = 0x1000,
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},
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[pbn_titan_8_4000000] = {
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.flags = FL_BASE0,
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.num_ports = 8,
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.base_baud = 4000000,
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.uart_offset = 0x200,
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.first_offset = 0x1000,
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},
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[pbn_moxa8250_2p] = {
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[pbn_moxa8250_2p] = {
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.flags = FL_BASE1,
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.flags = FL_BASE1,
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.num_ports = 2,
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.num_ports = 2,
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@@ -4721,22 +4753,22 @@ static const struct pci_device_id serial_pci_tbl[] = {
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pbn_b0_4_921600 },
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pbn_b0_4_921600 },
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_oxsemi_1_4000000 },
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pbn_titan_1_4000000 },
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_oxsemi_2_4000000 },
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pbn_titan_2_4000000 },
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_oxsemi_4_4000000 },
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pbn_titan_4_4000000 },
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_oxsemi_8_4000000 },
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pbn_titan_8_4000000 },
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_oxsemi_2_4000000 },
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pbn_titan_2_4000000 },
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_oxsemi_2_4000000 },
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pbn_titan_2_4000000 },
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
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{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b0_bt_2_921600 },
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pbn_b0_bt_2_921600 },
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