Merge tag 'topic/drm-misc-2016-11-10' of git://anongit.freedesktop.org/drm-intel into drm-next
- better atomic state debugging from Rob - fence prep from gustavo - sumits flushed out his backlog of pending dma-buf/fence patches from various people - drm_mm leak debugging plus trying to appease Kconfig (Chris) - a few misc things all over * tag 'topic/drm-misc-2016-11-10' of git://anongit.freedesktop.org/drm-intel: (35 commits) drm: Make DRM_DEBUG_MM depend on STACKTRACE_SUPPORT drm/i915: Restrict DRM_DEBUG_MM automatic selection drm: Restrict stackdepot usage to builtin drm.ko drm/msm: module param to dump state on error irq drm/msm/mdp5: add atomic_print_state support drm/atomic: add debugfs file to dump out atomic state drm/atomic: add new drm_debug bit to dump atomic state drm: add helpers to go from plane state to drm_rect drm: add helper for printing to log or seq_file drm: helper macros to print composite types reservation: revert "wait only with non-zero timeout specified (v3)" v2 drm/ttm: fix ttm_bo_wait dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) dma-buf/fence: make timeout handling in fence_default_wait consistent (v2) drm/amdgpu: add the interface of waiting multiple fences (v4) dma-buf: return index of the first signaled fence (v2) MAINTAINERS: update Sync File Framework files dma-buf/sw_sync: put fence reference from the fence creation dma-buf/sw_sync: mark sync_timeline_create() static drm: Add stackdepot include for DRM_DEBUG_MM ...
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@@ -50,6 +50,7 @@ extern "C" {
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#define DRM_AMDGPU_WAIT_CS 0x09
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#define DRM_AMDGPU_GEM_OP 0x10
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#define DRM_AMDGPU_GEM_USERPTR 0x11
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#define DRM_AMDGPU_WAIT_FENCES 0x12
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#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
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#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
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@@ -63,6 +64,7 @@ extern "C" {
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#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
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#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
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#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
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#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
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#define AMDGPU_GEM_DOMAIN_CPU 0x1
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#define AMDGPU_GEM_DOMAIN_GTT 0x2
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@@ -307,6 +309,32 @@ union drm_amdgpu_wait_cs {
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struct drm_amdgpu_wait_cs_out out;
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};
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struct drm_amdgpu_fence {
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__u32 ctx_id;
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__u32 ip_type;
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__u32 ip_instance;
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__u32 ring;
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__u64 seq_no;
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};
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struct drm_amdgpu_wait_fences_in {
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/** This points to uint64_t * which points to fences */
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__u64 fences;
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__u32 fence_count;
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__u32 wait_all;
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__u64 timeout_ns;
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};
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struct drm_amdgpu_wait_fences_out {
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__u32 status;
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__u32 first_signaled;
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};
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union drm_amdgpu_wait_fences {
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struct drm_amdgpu_wait_fences_in in;
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struct drm_amdgpu_wait_fences_out out;
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};
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#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
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#define AMDGPU_GEM_OP_SET_PLACEMENT 1
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@@ -47,7 +47,15 @@ extern "C" {
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#define DRM_MODE_TYPE_DRIVER (1<<6)
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/* Video mode flags */
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/* bit compatible with the xorg definitions. */
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/* bit compatible with the xrandr RR_ definitions (bits 0-13)
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*
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* ABI warning: Existing userspace really expects
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* the mode flags to match the xrandr definitions. Any
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* changes that don't match the xrandr definitions will
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* likely need a new client cap or some other mechanism
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* to avoid breaking existing userspace. This includes
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* allocating new flags in the previously unused bits!
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*/
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#define DRM_MODE_FLAG_PHSYNC (1<<0)
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#define DRM_MODE_FLAG_NHSYNC (1<<1)
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#define DRM_MODE_FLAG_PVSYNC (1<<2)
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