usb: phy: tegra: Tegra30 support
The Tegra30 USB PHY is a bit different than the Tegra20 PHY: - The EHCI controller supports the HOSTPC register extension, and some of the fields that the PHY needs to modify (PHCD and PTS) have moved to the new HOSTPC register. - Some of the UTMI PLL configuration registers have moved from the USB register space to the Clock-And-Reset controller space. In Tegra30 the clock driver is responsible for configuring the UTMI PLL. - The USBMODE register must be explicitly written to enter host mode. - Certain PHY parameters need to be programmed for optimal signal quality. Support for this will be added in the next patch. The new tegra_phy_soc_config structure is added to describe the differences between the SoCs. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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Felipe Balbi

parent
f5833a0bde
commit
3e635202ce
@@ -18,6 +18,24 @@
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#include <linux/clk.h>
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#include <linux/usb/otg.h>
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/*
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* utmi_pll_config_in_car_module: true if the UTMI PLL configuration registers
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* should be set up by clk-tegra, false if by the PHY code
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* has_hostpc: true if the USB controller has the HOSTPC extension, which
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* changes the location of the PHCD and PTS fields
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* requires_usbmode_setup: true if the USBMODE register needs to be set to
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* enter host mode
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* requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level
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* and hsdiscon_level should be set for adequate signal quality
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*/
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struct tegra_phy_soc_config {
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bool utmi_pll_config_in_car_module;
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bool has_hostpc;
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bool requires_usbmode_setup;
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bool requires_extra_tuning_parameters;
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};
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struct tegra_utmip_config {
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u8 hssync_start_delay;
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u8 elastic_limit;
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@@ -47,6 +65,7 @@ struct tegra_usb_phy {
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struct regulator *vbus;
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enum usb_dr_mode mode;
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void *config;
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const struct tegra_phy_soc_config *soc_config;
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struct usb_phy *ulpi;
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struct usb_phy u_phy;
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bool is_legacy_phy;
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