xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clk: imx8mm: Define gates for pll1/2 fixed dividers

Browse Source 
On imx8mm there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.

Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Leonard Crestez
2019-10-16 11:57:39 +00:00
committed by Shawn Guo
parent b04383b6a5
commit 3e4947acad
2 changed files with 56 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
include/dt-bindings/clock/imx8mm-clock.h
View File

@@ -248,6 +248,23 @@
#define IMX8MM_CLK_SNVS_ROOT 228
#define IMX8MM_CLK_GIC 229
#define IMX8MM_CLK_END 230
#define IMX8MM_SYS_PLL1_40M_CG 230
#define IMX8MM_SYS_PLL1_80M_CG 231
#define IMX8MM_SYS_PLL1_100M_CG 232
#define IMX8MM_SYS_PLL1_133M_CG 233
#define IMX8MM_SYS_PLL1_160M_CG 234
#define IMX8MM_SYS_PLL1_200M_CG 235
#define IMX8MM_SYS_PLL1_266M_CG 236
#define IMX8MM_SYS_PLL1_400M_CG 237
#define IMX8MM_SYS_PLL2_50M_CG 238
#define IMX8MM_SYS_PLL2_100M_CG 239
#define IMX8MM_SYS_PLL2_125M_CG 240
#define IMX8MM_SYS_PLL2_166M_CG 241
#define IMX8MM_SYS_PLL2_200M_CG 242
#define IMX8MM_SYS_PLL2_250M_CG 243
#define IMX8MM_SYS_PLL2_333M_CG 244
#define IMX8MM_SYS_PLL2_500M_CG 245
#define IMX8MM_CLK_END 246
#endif