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ARM: entry: data abort: arrange for CPU abort helpers to take pc/psr in r4/r5

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Re-jig the CPU abort helpers to take the PC/PSR in r4/r5 rather
than r2/r3.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
2011-06-26 14:35:07 +01:00
parent 8dfe7ac96f
commit 3e287bec6f
10 changed files with 38 additions and 46 deletions
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8
arch/arm/mm/abort-ev4.S
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@@ -3,8 +3,8 @@
/*
* Function: v4_early_abort
*
* Params : r2 = address of aborted instruction
* : r3 = saved SPSR
* Params : r4 = aborted context pc
* : r5 = aborted context psr
*
* Returns : r0 = address of abort
* : r1 = FSR, bit 11 = write
@@ -21,10 +21,8 @@
ENTRY(v4_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
ldr r3, [r2] @ read aborted ARM instruction
ldr r3, [r4] @ read aborted ARM instruction
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r3, #1 << 20 @ L = 1 -> write?
orreq r1, r1, #1 << 11 @ yes.
mov pc, lr