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ARM: at91: at91 based machines specify their own irq handler at run time

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SOC_AT91SAM9 selects MULTI_IRQ_HANDLER in order to let machines specify their
own IRQ handler at run time.

Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Ludovic Desroches
2012-06-11 15:38:03 +02:00
committed by Nicolas Ferre
parent 3a6b37134c
commit 3e13546674
40 changed files with 98 additions and 27 deletions
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2
arch/arm/mach-at91/include/mach/at91_aic.h
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@@ -65,4 +65,6 @@ extern void __iomem *at91_aic_base;
#define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */
#define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */
void at91_aic_handle_irq(struct pt_regs *regs);
#endif

27
arch/arm/mach-at91/include/mach/entry-macro.S
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@@ -1,27 +0,0 @@
/*
* arch/arm/mach-at91/include/mach/entry-macro.S
*
* Copyright (C) 2003-2005 SAN People
*
* Low-level IRQ helper macros for AT91RM9200 platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <mach/hardware.h>
#include <mach/at91_aic.h>
.macro get_irqnr_preamble, base, tmp
ldr \base, =at91_aic_base @ base virtual address of AIC peripheral
ldr \base, [\base]
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number
teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now.
.endm