bcm63xx_enet: add support Broadcom BCM6345 Ethernet
This patch adds support for the Broadcom BCM6345 SoC Ethernet. BCM6345
has a slightly different and older DMA engine which requires the
following modifications:
- the width of the DMA channels on BCM6345 is 64 bytes vs 16 bytes,
which means that the helpers enet_dma{c,s} need to account for this
channel width and we can no longer use macros
- BCM6345 DMA engine does not have any internal SRAM for transfering
buffers
- BCM6345 buffer allocation and flow control is not per-channel but
global (done in RSET_ENETDMA)
- the DMA engine bits are right-shifted by 3 compared to other DMA
generations
- the DMA enable/interrupt masks are a little different (we need to
enabled more bits for 6345)
- some register have the same meaning but are offsetted in the ENET_DMAC
space so a lookup table is required to return the proper offset
The MAC itself is identical and requires no modifications to work.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Florian Fainelli
committed by
David S. Miller
David S. Miller
parent
ca4ec90b31
commit
3dc6475c0c
@@ -174,6 +174,7 @@ enum bcm63xx_regs_set {
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#define BCM_6368_RSET_SPI_SIZE 1804
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#define RSET_ENET_SIZE 2048
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#define RSET_ENETDMA_SIZE 256
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#define RSET_6345_ENETDMA_SIZE 64
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#define RSET_ENETDMAC_SIZE(chans) (16 * (chans))
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#define RSET_ENETDMAS_SIZE(chans) (16 * (chans))
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#define RSET_ENETSW_SIZE 65536
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@@ -300,7 +301,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_USBDMA_BASE (0xfffe2800)
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#define BCM_6345_ENET0_BASE (0xfffe1800)
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#define BCM_6345_ENETDMA_BASE (0xfffe2800)
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#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
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#define BCM_6345_ENETDMAC_BASE (0xfffe2840)
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#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
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#define BCM_6345_ENETSW_BASE (0xdeadbeef)
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#define BCM_6345_PCMCIA_BASE (0xfffe2028)
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@@ -4,6 +4,8 @@
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#include <linux/if_ether.h>
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#include <linux/init.h>
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#include <bcm63xx_regs.h>
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/*
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* on board ethernet platform data
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*/
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@@ -37,6 +39,21 @@ struct bcm63xx_enet_platform_data {
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int phy_id, int reg),
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void (*mii_write)(struct net_device *dev,
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int phy_id, int reg, int val));
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/* DMA channel enable mask */
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u32 dma_chan_en_mask;
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/* DMA channel interrupt mask */
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u32 dma_chan_int_mask;
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/* DMA engine has internal SRAM */
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bool dma_has_sram;
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/* DMA channel register width */
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unsigned int dma_chan_width;
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/* DMA descriptor shift */
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unsigned int dma_desc_shift;
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};
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/*
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@@ -63,6 +80,18 @@ struct bcm63xx_enetsw_platform_data {
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char mac_addr[ETH_ALEN];
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int num_ports;
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struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
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/* DMA channel enable mask */
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u32 dma_chan_en_mask;
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/* DMA channel interrupt mask */
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u32 dma_chan_int_mask;
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/* DMA channel register width */
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unsigned int dma_chan_width;
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/* DMA engine has internal SRAM */
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bool dma_has_sram;
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};
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int __init bcm63xx_enet_register(int unit,
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@@ -70,4 +99,69 @@ int __init bcm63xx_enet_register(int unit,
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int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
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enum bcm63xx_regs_enetdmac {
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ENETDMAC_CHANCFG,
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ENETDMAC_IR,
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ENETDMAC_IRMASK,
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ENETDMAC_MAXBURST,
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ENETDMAC_BUFALLOC,
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ENETDMAC_RSTART,
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ENETDMAC_FC,
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ENETDMAC_LEN,
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};
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static inline unsigned long bcm63xx_enetdmacreg(enum bcm63xx_regs_enetdmac reg)
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{
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#ifdef BCMCPU_RUNTIME_DETECT
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extern const unsigned long *bcm63xx_regs_enetdmac;
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return bcm63xx_regs_enetdmac[reg];
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#else
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#ifdef CONFIG_BCM63XX_CPU_6345
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switch (reg) {
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case ENETDMAC_CHANCFG:
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return ENETDMA_6345_CHANCFG_REG;
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case ENETDMAC_IR:
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return ENETDMA_6345_IR_REG;
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case ENETDMAC_IRMASK:
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return ENETDMA_6345_IRMASK_REG;
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case ENETDMAC_MAXBURST:
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return ENETDMA_6345_MAXBURST_REG;
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case ENETDMAC_BUFALLOC:
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return ENETDMA_6345_BUFALLOC_REG;
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case ENETDMAC_RSTART:
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return ENETDMA_6345_RSTART_REG;
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case ENETDMAC_FC:
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return ENETDMA_6345_FC_REG;
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case ENETDMAC_LEN:
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return ENETDMA_6345_LEN_REG;
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}
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#endif
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#if defined(CONFIG_BCM63XX_CPU_6328) || \
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defined(CONFIG_BCM63XX_CPU_6338) || \
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defined(CONFIG_BCM63XX_CPU_6348) || \
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defined(CONFIG_BCM63XX_CPU_6358) || \
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defined(CONFIG_BCM63XX_CPU_6362) || \
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defined(CONFIG_BCM63XX_CPU_6368)
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switch (reg) {
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case ENETDMAC_CHANCFG:
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return ENETDMAC_CHANCFG_REG;
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case ENETDMAC_IR:
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return ENETDMAC_IR_REG;
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case ENETDMAC_IRMASK:
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return ENETDMAC_IRMASK_REG;
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case ENETDMAC_MAXBURST:
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return ENETDMAC_MAXBURST_REG;
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case ENETDMAC_BUFALLOC:
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case ENETDMAC_RSTART:
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case ENETDMAC_FC:
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case ENETDMAC_LEN:
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return 0;
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}
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#endif
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#endif
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return 0;
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}
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#endif /* ! BCM63XX_DEV_ENET_H_ */
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@@ -727,6 +727,8 @@
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/*************************************************************************
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* _REG relative to RSET_ENETDMA
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*************************************************************************/
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#define ENETDMA_CHAN_WIDTH 0x10
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#define ENETDMA_6345_CHAN_WIDTH 0x40
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/* Controller Configuration Register */
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#define ENETDMA_CFG_REG (0x0)
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@@ -782,31 +784,56 @@
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/* State Ram Word 4 */
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#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
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/* Broadcom 6345 ENET DMA definitions */
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#define ENETDMA_6345_CHANCFG_REG (0x00)
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#define ENETDMA_6345_MAXBURST_REG (0x40)
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#define ENETDMA_6345_RSTART_REG (0x08)
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#define ENETDMA_6345_LEN_REG (0x0C)
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#define ENETDMA_6345_IR_REG (0x14)
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#define ENETDMA_6345_IRMASK_REG (0x18)
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#define ENETDMA_6345_FC_REG (0x1C)
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#define ENETDMA_6345_BUFALLOC_REG (0x20)
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/* Shift down for EOP, SOP and WRAP bits */
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#define ENETDMA_6345_DESC_SHIFT (3)
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/*************************************************************************
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* _REG relative to RSET_ENETDMAC
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*************************************************************************/
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/* Channel Configuration register */
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#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
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#define ENETDMAC_CHANCFG_REG (0x0)
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#define ENETDMAC_CHANCFG_EN_SHIFT 0
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#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT)
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#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
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#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
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#define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
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#define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
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#define ENETDMAC_CHANCFG_CHAINING_SHIFT 2
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#define ENETDMAC_CHANCFG_CHAINING_MASK (1 << ENETDMAC_CHANCFG_CHAINING_SHIFT)
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#define ENETDMAC_CHANCFG_WRAP_EN_SHIFT 3
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#define ENETDMAC_CHANCFG_WRAP_EN_MASK (1 << ENETDMAC_CHANCFG_WRAP_EN_SHIFT)
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#define ENETDMAC_CHANCFG_FLOWC_EN_SHIFT 4
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#define ENETDMAC_CHANCFG_FLOWC_EN_MASK (1 << ENETDMAC_CHANCFG_FLOWC_EN_SHIFT)
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/* Interrupt Control/Status register */
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#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
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#define ENETDMAC_IR_REG (0x4)
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#define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
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#define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
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#define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
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/* Interrupt Mask register */
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#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
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#define ENETDMAC_IRMASK_REG (0x8)
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/* Maximum Burst Length */
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#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
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#define ENETDMAC_MAXBURST_REG (0xc)
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/*************************************************************************
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@@ -814,16 +841,16 @@
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*************************************************************************/
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/* Ring Start Address register */
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#define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
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#define ENETDMAS_RSTART_REG (0x0)
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/* State Ram Word 2 */
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#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
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#define ENETDMAS_SRAM2_REG (0x4)
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/* State Ram Word 3 */
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#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
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#define ENETDMAS_SRAM3_REG (0x8)
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/* State Ram Word 4 */
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#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
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#define ENETDMAS_SRAM4_REG (0xc)
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/*************************************************************************
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