[ARM] 4457/2: davinci: GPIO support
Support GPIO driver for TI DaVinci SoC Signed-off-by: Vladimir Barinov <vbarino@ru.mvista.com> Acked-by: David Brownell <david-b@pacbell.net> Acked-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Vladimir Barinov
committed by
Russell King
Russell King
parent
3e062b07ad
commit
3d9edf09d4
286
arch/arm/mach-davinci/gpio.c
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286
arch/arm/mach-davinci/gpio.c
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/*
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* TI DaVinci GPIO Support
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*
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* Copyright (c) 2006 David Brownell
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* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/bitops.h>
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#include <asm/arch/irqs.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/gpio.h>
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#include <asm/mach/irq.h>
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static DEFINE_SPINLOCK(gpio_lock);
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static DECLARE_BITMAP(gpio_in_use, DAVINCI_N_GPIO);
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int gpio_request(unsigned gpio, const char *tag)
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{
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if (gpio >= DAVINCI_N_GPIO)
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return -EINVAL;
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if (test_and_set_bit(gpio, gpio_in_use))
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return -EBUSY;
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return 0;
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}
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EXPORT_SYMBOL(gpio_request);
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void gpio_free(unsigned gpio)
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{
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if (gpio >= DAVINCI_N_GPIO)
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return;
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clear_bit(gpio, gpio_in_use);
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}
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EXPORT_SYMBOL(gpio_free);
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/* create a non-inlined version */
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static struct gpio_controller *__iomem gpio2controller(unsigned gpio)
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{
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return __gpio_to_controller(gpio);
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}
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/*
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* Assuming the pin is muxed as a gpio output, set its output value.
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*/
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void __gpio_set(unsigned gpio, int value)
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{
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struct gpio_controller *__iomem g = gpio2controller(gpio);
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__raw_writel(__gpio_mask(gpio), value ? &g->set_data : &g->clr_data);
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}
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EXPORT_SYMBOL(__gpio_set);
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/*
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* Read the pin's value (works even if it's set up as output);
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* returns zero/nonzero.
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*
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* Note that changes are synched to the GPIO clock, so reading values back
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* right after you've set them may give old values.
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*/
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int __gpio_get(unsigned gpio)
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{
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struct gpio_controller *__iomem g = gpio2controller(gpio);
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return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data));
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}
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EXPORT_SYMBOL(__gpio_get);
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/*--------------------------------------------------------------------------*/
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/*
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* board setup code *MUST* set PINMUX0 and PINMUX1 as
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* needed, and enable the GPIO clock.
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*/
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int gpio_direction_input(unsigned gpio)
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{
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struct gpio_controller *__iomem g = gpio2controller(gpio);
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u32 temp;
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u32 mask;
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if (!g)
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return -EINVAL;
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spin_lock(&gpio_lock);
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mask = __gpio_mask(gpio);
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temp = __raw_readl(&g->dir);
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temp |= mask;
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__raw_writel(temp, &g->dir);
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spin_unlock(&gpio_lock);
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_input);
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int gpio_direction_output(unsigned gpio, int value)
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{
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struct gpio_controller *__iomem g = gpio2controller(gpio);
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u32 temp;
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u32 mask;
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if (!g)
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return -EINVAL;
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spin_lock(&gpio_lock);
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mask = __gpio_mask(gpio);
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temp = __raw_readl(&g->dir);
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temp &= ~mask;
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__raw_writel(mask, value ? &g->set_data : &g->clr_data);
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__raw_writel(temp, &g->dir);
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spin_unlock(&gpio_lock);
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_output);
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/*
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* We expect irqs will normally be set up as input pins, but they can also be
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* used as output pins ... which is convenient for testing.
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*
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* NOTE: GPIO0..GPIO7 also have direct INTC hookups, which work in addition
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* to their GPIOBNK0 irq (but with a bit less overhead). But we don't have
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* a good way to hook those up ...
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*
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* All those INTC hookups (GPIO0..GPIO7 plus five IRQ banks) can also
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* serve as EDMA event triggers.
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*/
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static void gpio_irq_disable(unsigned irq)
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{
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struct gpio_controller *__iomem g = get_irq_chip_data(irq);
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u32 mask = __gpio_mask(irq_to_gpio(irq));
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__raw_writel(mask, &g->clr_falling);
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__raw_writel(mask, &g->clr_rising);
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}
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static void gpio_irq_enable(unsigned irq)
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{
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struct gpio_controller *__iomem g = get_irq_chip_data(irq);
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u32 mask = __gpio_mask(irq_to_gpio(irq));
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if (irq_desc[irq].status & IRQ_TYPE_EDGE_FALLING)
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__raw_writel(mask, &g->set_falling);
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if (irq_desc[irq].status & IRQ_TYPE_EDGE_RISING)
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__raw_writel(mask, &g->set_rising);
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}
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static int gpio_irq_type(unsigned irq, unsigned trigger)
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{
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struct gpio_controller *__iomem g = get_irq_chip_data(irq);
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u32 mask = __gpio_mask(irq_to_gpio(irq));
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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return -EINVAL;
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irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
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irq_desc[irq].status |= trigger;
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__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
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? &g->set_falling : &g->clr_falling);
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__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
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? &g->set_rising : &g->clr_rising);
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return 0;
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}
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static struct irq_chip gpio_irqchip = {
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.name = "GPIO",
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.enable = gpio_irq_enable,
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.disable = gpio_irq_disable,
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.set_type = gpio_irq_type,
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};
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static void
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gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct gpio_controller *__iomem g = get_irq_chip_data(irq);
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u32 mask = 0xffff;
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/* we only care about one bank */
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if (irq & 1)
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mask <<= 16;
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/* temporarily mask (level sensitive) parent IRQ */
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desc->chip->ack(irq);
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while (1) {
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u32 status;
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struct irq_desc *gpio;
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int n;
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int res;
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/* ack any irqs */
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status = __raw_readl(&g->intstat) & mask;
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if (!status)
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break;
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__raw_writel(status, &g->intstat);
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if (irq & 1)
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status >>= 16;
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/* now demux them to the right lowlevel handler */
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n = (int)get_irq_data(irq);
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gpio = &irq_desc[n];
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while (status) {
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res = ffs(status);
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n += res;
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gpio += res;
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desc_handle_irq(n - 1, gpio - 1);
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status >>= res;
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}
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}
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desc->chip->unmask(irq);
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/* now it may re-trigger */
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}
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/*
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* NOTE: for suspend/resume, probably best to make a sysdev (and class)
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* with its suspend/resume calls hooking into the results of the set_wake()
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* calls ... so if no gpios are wakeup events the clock can be disabled,
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* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
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* can be set appropriately for GPIOV33 pins.
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*/
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static int __init davinci_gpio_irq_setup(void)
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{
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unsigned gpio, irq, bank;
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struct clk *clk;
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clk = clk_get(NULL, "gpio");
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if (IS_ERR(clk)) {
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printk(KERN_ERR "Error %ld getting gpio clock?\n",
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PTR_ERR(clk));
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return 0;
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}
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clk_enable(clk);
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for (gpio = 0, irq = gpio_to_irq(0), bank = IRQ_GPIOBNK0;
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gpio < DAVINCI_N_GPIO; bank++) {
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struct gpio_controller *__iomem g = gpio2controller(gpio);
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unsigned i;
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__raw_writel(~0, &g->clr_falling);
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__raw_writel(~0, &g->clr_rising);
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/* set up all irqs in this bank */
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set_irq_chained_handler(bank, gpio_irq_handler);
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set_irq_chip_data(bank, g);
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set_irq_data(bank, (void *)irq);
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for (i = 0; i < 16 && gpio < DAVINCI_N_GPIO;
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i++, irq++, gpio++) {
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set_irq_chip(irq, &gpio_irqchip);
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set_irq_chip_data(irq, g);
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set_irq_handler(irq, handle_simple_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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}
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/* BINTEN -- per-bank interrupt enable. genirq would also let these
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* bits be set/cleared dynamically.
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*/
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__raw_writel(0x1f, (void *__iomem)
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IO_ADDRESS(DAVINCI_GPIO_BASE + 0x08));
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printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
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return 0;
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}
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arch_initcall(davinci_gpio_irq_setup);
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