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Merge branch 'linus' into irq/numa

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Conflicts:
	arch/mips/sibyte/bcm1480/irq.c
	arch/mips/sibyte/sb1250/irq.c

Merge reason: we gathered a few conflicts plus update to latest upstream fixes.

Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar
2009-06-01 21:06:21 +02:00
부모 abfe0af981 d9244b5d2f
커밋 3d58f48ba0
758개의 변경된 파일과 19625개의 추가작업 그리고 5339개의 파일을 삭제
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46
arch/powerpc/sysdev/fsl_soc.c
파일 보기

@@ -208,52 +208,6 @@ static int __init of_add_fixed_phys(void)
arch_initcall(of_add_fixed_phys);
#endif /* CONFIG_FIXED_PHY */
#ifdef CONFIG_PPC_83xx
static int __init mpc83xx_wdt_init(void)
{
struct resource r;
struct device_node *np;
struct platform_device *dev;
u32 freq = fsl_get_sys_freq();
int ret;
np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt");
if (!np) {
ret = -ENODEV;
goto nodev;
}
memset(&r, 0, sizeof(r));
ret = of_address_to_resource(np, 0, &r);
if (ret)
goto err;
dev = platform_device_register_simple("mpc83xx_wdt", 0, &r, 1);
if (IS_ERR(dev)) {
ret = PTR_ERR(dev);
goto err;
}
ret = platform_device_add_data(dev, &freq, sizeof(freq));
if (ret)
goto unreg;
of_node_put(np);
return 0;
unreg:
platform_device_unregister(dev);
err:
of_node_put(np);
nodev:
return ret;
}
arch_initcall(mpc83xx_wdt_init);
#endif
static enum fsl_usb2_phy_modes determine_usb_phy(const char *phy_type)
{
if (!phy_type)

16
arch/powerpc/sysdev/mpic.c
파일 보기

@@ -1059,13 +1059,6 @@ struct mpic * __init mpic_alloc(struct device_node *node,
memset(mpic, 0, sizeof(struct mpic));
mpic->name = name;
mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
isu_size, &mpic_host_ops,
flags & MPIC_LARGE_VECTORS ? 2048 : 256);
if (mpic->irqhost == NULL)
return NULL;
mpic->irqhost->host_data = mpic;
mpic->hc_irq = mpic_irq_chip;
mpic->hc_irq.typename = name;
if (flags & MPIC_PRIMARY)
@@ -1215,6 +1208,15 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
mpic->isu_mask = (1 << mpic->isu_shift) - 1;
mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
isu_size ? isu_size : mpic->num_sources,
&mpic_host_ops,
flags & MPIC_LARGE_VECTORS ? 2048 : 256);
if (mpic->irqhost == NULL)
return NULL;
mpic->irqhost->host_data = mpic;
/* Display version */
switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
case 1:

117
arch/powerpc/sysdev/xilinx_intc.c
파일 보기

@@ -41,8 +41,32 @@
static struct irq_host *master_irqhost;
#define XILINX_INTC_MAXIRQS (32)
/* The following table allows the interrupt type, edge or level,
* to be cached after being read from the device tree until the interrupt
* is mapped
*/
static int xilinx_intc_typetable[XILINX_INTC_MAXIRQS];
/* Map the interrupt type from the device tree to the interrupt types
* used by the interrupt subsystem
*/
static unsigned char xilinx_intc_map_senses[] = {
IRQ_TYPE_EDGE_RISING,
IRQ_TYPE_EDGE_FALLING,
IRQ_TYPE_LEVEL_HIGH,
IRQ_TYPE_LEVEL_LOW,
};
/*
* IRQ Chip operations
* The interrupt controller is setup such that it doesn't work well with
* the level interrupt handler in the kernel because the handler acks the
* interrupt before calling the application interrupt handler. To deal with
* that, we use 2 different irq chips so that different functions can be
* used for level and edge type interrupts.
*
* IRQ Chip common (across level and edge) operations
*/
static void xilinx_intc_mask(unsigned int virq)
{
@@ -52,15 +76,54 @@ static void xilinx_intc_mask(unsigned int virq)
out_be32(regs + XINTC_CIE, 1 << irq);
}
static void xilinx_intc_unmask(unsigned int virq)
static int xilinx_intc_set_type(unsigned int virq, unsigned int flow_type)
{
struct irq_desc *desc = get_irq_desc(virq);
desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
desc->status |= IRQ_LEVEL;
return 0;
}
/*
* IRQ Chip level operations
*/
static void xilinx_intc_level_unmask(unsigned int virq)
{
int irq = virq_to_hw(virq);
void * regs = get_irq_chip_data(virq);
pr_debug("unmask: %d\n", irq);
out_be32(regs + XINTC_SIE, 1 << irq);
/* ack level irqs because they can't be acked during
* ack function since the handle_level_irq function
* acks the irq before calling the inerrupt handler
*/
out_be32(regs + XINTC_IAR, 1 << irq);
}
static void xilinx_intc_ack(unsigned int virq)
static struct irq_chip xilinx_intc_level_irqchip = {
.typename = "Xilinx Level INTC",
.mask = xilinx_intc_mask,
.mask_ack = xilinx_intc_mask,
.unmask = xilinx_intc_level_unmask,
.set_type = xilinx_intc_set_type,
};
/*
* IRQ Chip edge operations
*/
static void xilinx_intc_edge_unmask(unsigned int virq)
{
int irq = virq_to_hw(virq);
void *regs = get_irq_chip_data(virq);
pr_debug("unmask: %d\n", irq);
out_be32(regs + XINTC_SIE, 1 << irq);
}
static void xilinx_intc_edge_ack(unsigned int virq)
{
int irq = virq_to_hw(virq);
void * regs = get_irq_chip_data(virq);
@@ -68,27 +131,60 @@ static void xilinx_intc_ack(unsigned int virq)
out_be32(regs + XINTC_IAR, 1 << irq);
}
static struct irq_chip xilinx_intc_irqchip = {
.typename = "Xilinx INTC",
static struct irq_chip xilinx_intc_edge_irqchip = {
.typename = "Xilinx Edge INTC",
.mask = xilinx_intc_mask,
.unmask = xilinx_intc_unmask,
.ack = xilinx_intc_ack,
.unmask = xilinx_intc_edge_unmask,
.ack = xilinx_intc_edge_ack,
.set_type = xilinx_intc_set_type,
};
/*
* IRQ Host operations
*/
/**
* xilinx_intc_xlate - translate virq# from device tree interrupts property
*/
static int xilinx_intc_xlate(struct irq_host *h, struct device_node *ct,
u32 *intspec, unsigned int intsize,
irq_hw_number_t *out_hwirq,
unsigned int *out_flags)
{
if ((intsize < 2) || (intspec[0] >= XILINX_INTC_MAXIRQS))
return -EINVAL;
/* keep a copy of the interrupt type til the interrupt is mapped
*/
xilinx_intc_typetable[intspec[0]] = xilinx_intc_map_senses[intspec[1]];
/* Xilinx uses 2 interrupt entries, the 1st being the h/w
* interrupt number, the 2nd being the interrupt type, edge or level
*/
*out_hwirq = intspec[0];
*out_flags = xilinx_intc_map_senses[intspec[1]];
return 0;
}
static int xilinx_intc_map(struct irq_host *h, unsigned int virq,
irq_hw_number_t irq)
{
set_irq_chip_data(virq, h->host_data);
set_irq_chip_and_handler(virq, &xilinx_intc_irqchip, handle_level_irq);
set_irq_type(virq, IRQ_TYPE_NONE);
if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH ||
xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) {
set_irq_chip_and_handler(virq, &xilinx_intc_level_irqchip,
handle_level_irq);
} else {
set_irq_chip_and_handler(virq, &xilinx_intc_edge_irqchip,
handle_edge_irq);
}
return 0;
}
static struct irq_host_ops xilinx_intc_ops = {
.map = xilinx_intc_map,
.xlate = xilinx_intc_xlate,
};
struct irq_host * __init
@@ -116,7 +212,8 @@ xilinx_intc_init(struct device_node *np)
out_be32(regs + XINTC_MER, 0x3UL); /* Turn on the Master Enable. */
/* Allocate and initialize an irq_host structure. */
irq = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, 32, &xilinx_intc_ops, -1);
irq = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, XILINX_INTC_MAXIRQS,
&xilinx_intc_ops, -1);
if (!irq)
panic(__FILE__ ": Cannot allocate IRQ host\n");
irq->host_data = regs;