cxl: Export library to support IBM XSL
This patch exports a in-kernel 'library' API which can be called by other drivers to help interacting with an IBM XSL on a POWER9 system. The XSL (Translation Service Layer) is a stripped down version of the PSL (Power Service Layer) used in some cards such as the Mellanox CX5. Like the PSL, it implements the CAIA architecture, but has a number of differences, mostly in it's implementation dependent registers. The XSL also uses a special DMA cxl mode, which uses a slightly different init sequence for the CAPP and PHB. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Christophe Lombard
committed by
Michael Ellerman
Michael Ellerman
parent
218ea31039
commit
3ced8d7300
133
include/misc/cxllib.h
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133
include/misc/cxllib.h
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/*
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* Copyright 2017 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _MISC_CXLLIB_H
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#define _MISC_CXLLIB_H
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#include <linux/pci.h>
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#include <asm/reg.h>
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/*
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* cxl driver exports a in-kernel 'library' API which can be called by
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* other drivers to help interacting with an IBM XSL.
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*/
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/*
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* tells whether capi is supported on the PCIe slot where the
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* device is seated
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*
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* Input:
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* dev: device whose slot needs to be checked
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* flags: 0 for the time being
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*/
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bool cxllib_slot_is_supported(struct pci_dev *dev, unsigned long flags);
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/*
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* Returns the configuration parameters to be used by the XSL or device
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*
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* Input:
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* dev: device, used to find PHB
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* Output:
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* struct cxllib_xsl_config:
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* version
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* capi BAR address, i.e. 0x2000000000000-0x2FFFFFFFFFFFF
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* capi BAR size
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* data send control (XSL_DSNCTL)
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* dummy read address (XSL_DRA)
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*/
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#define CXL_XSL_CONFIG_VERSION1 1
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struct cxllib_xsl_config {
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u32 version; /* format version for register encoding */
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u32 log_bar_size;/* log size of the capi_window */
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u64 bar_addr; /* address of the start of capi window */
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u64 dsnctl; /* matches definition of XSL_DSNCTL */
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u64 dra; /* real address that can be used for dummy read */
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};
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int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg);
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/*
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* Activate capi for the pci host bridge associated with the device.
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* Can be extended to deactivate once we know how to do it.
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* Device must be ready to accept messages from the CAPP unit and
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* respond accordingly (TLB invalidates, ...)
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*
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* PHB is switched to capi mode through calls to skiboot.
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* CAPP snooping is activated
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*
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* Input:
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* dev: device whose PHB should switch mode
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* mode: mode to switch to i.e. CAPI or PCI
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* flags: options related to the mode
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*/
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enum cxllib_mode {
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CXL_MODE_CXL,
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CXL_MODE_PCI,
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};
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#define CXL_MODE_NO_DMA 0
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#define CXL_MODE_DMA_TVT0 1
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#define CXL_MODE_DMA_TVT1 2
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int cxllib_switch_phb_mode(struct pci_dev *dev, enum cxllib_mode mode,
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unsigned long flags);
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/*
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* Set the device for capi DMA.
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* Define its dma_ops and dma offset so that allocations will be using TVT#1
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*
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* Input:
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* dev: device to set
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* flags: options. CXL_MODE_DMA_TVT1 should be used
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*/
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int cxllib_set_device_dma(struct pci_dev *dev, unsigned long flags);
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/*
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* Get the Process Element structure for the given thread
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*
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* Input:
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* task: task_struct for the context of the translation
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* translation_mode: whether addresses should be translated
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* Output:
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* attr: attributes to fill up the Process Element structure from CAIA
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*/
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struct cxllib_pe_attributes {
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u64 sr;
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u32 lpid;
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u32 tid;
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u32 pid;
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};
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#define CXL_TRANSLATED_MODE 0
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#define CXL_REAL_MODE 1
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int cxllib_get_PE_attributes(struct task_struct *task,
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unsigned long translation_mode, struct cxllib_pe_attributes *attr);
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/*
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* Handle memory fault.
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* Fault in all the pages of the specified buffer for the permissions
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* provided in ‘flags’
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*
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* Shouldn't be called from interrupt context
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*
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* Input:
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* mm: struct mm for the thread faulting the pages
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* addr: base address of the buffer to page in
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* size: size of the buffer to page in
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* flags: permission requested (DSISR_ISSTORE...)
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*/
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int cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags);
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#endif /* _MISC_CXLLIB_H */
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