drm/amd/display: clear underflow on optc unblank
[why] Underflow is asserted due to some timing condition which does not actually result in visible underflow (i.e. it occurs while blanked). [how] Force clear underflow occured bit whenver we unblank. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -359,20 +359,19 @@ void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enab
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static void optc1_unblank_crtc(struct timing_generator *optc)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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uint32_t vertical_interrupt_enable = 0;
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REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
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OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &vertical_interrupt_enable);
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/* temporary work around for vertical interrupt, once vertical interrupt enabled,
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* this check will be removed.
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*/
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if (vertical_interrupt_enable)
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optc1_set_blank_data_double_buffer(optc, true);
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REG_UPDATE_2(OTG_BLANK_CONTROL,
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OTG_BLANK_DATA_EN, 0,
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OTG_BLANK_DE_MODE, 0);
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/* W/A for automated testing
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* Automated testing will fail underflow test as there
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* sporadic underflows which occur during the optc blank
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* sequence. As a w/a, clear underflow on unblank.
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* This prevents the failure, but will not mask actual
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* underflow that affect real use cases.
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*/
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optc1_clear_optc_underflow(optc);
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}
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/**
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