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MIPS: Refactor dumping of TLB registers for r3k/r4k

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The TLB registers are dumped in a couble of places:
 - sysrq_tlbdump_single() - when dumping TLB state.
 - do_mcheck() - in response to a machine check error.

The main TLB registers also differ between r3k and r4k, but r4k appears
to be assumed.

Refactor this code into a dump_tlb_regs() function, implemented for both
r3k and r4k, and used by both of the above functions.

Fixes: d1e9a4f547 ("MIPS: Add SysRq operation to dump TLBs on all CPUs")
Suggested-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10721/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
James Hogan
2015-07-15 16:17:43 +01:00
committed by Ralf Baechle
parent 0f6ce77538
commit 3c865dd9c1
6 changed files with 34 additions and 28 deletions
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16
arch/mips/kernel/traps.c
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@@ -1523,7 +1523,6 @@ asmlinkage void do_watch(struct pt_regs *regs)
asmlinkage void do_mcheck(struct pt_regs *regs)
{
const int field = 2 * sizeof(unsigned long);
int multi_match = regs->cp0_status & ST0_TS;
enum ctx_state prev_state;
mm_segment_t old_fs = get_fs();
@@ -1532,19 +1531,8 @@ asmlinkage void do_mcheck(struct pt_regs *regs)
show_regs(regs);
if (multi_match) {
pr_err("Index : %0x\n", read_c0_index());
pr_err("Pagemask: %0x\n", read_c0_pagemask());
pr_err("EntryHi : %0*lx\n", field, read_c0_entryhi());
pr_err("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
pr_err("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
pr_err("Wired : %0x\n", read_c0_wired());
pr_err("Pagegrain: %0x\n", read_c0_pagegrain());
if (cpu_has_htw) {
pr_err("PWField : %0*lx\n", field, read_c0_pwfield());
pr_err("PWSize : %0*lx\n", field, read_c0_pwsize());
pr_err("PWCtl : %0x\n", read_c0_pwctl());
}
pr_err("\n");
dump_tlb_regs();
pr_info("\n");
dump_tlb_all();
}