regulator: uniphier: Add Pro5 USB3 VBUS support
Pro5 SoC has same scheme of USB3 VBUS as Pro4, so the data for Pro5 is equivalent to Pro4. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/1568080304-1572-1-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@@ -13,6 +13,7 @@ this layer. These clocks and resets should be described in each property.
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Required properties:
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- compatible: Should be
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"socionext,uniphier-pro4-usb3-regulator" - for Pro4 SoC
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"socionext,uniphier-pro5-usb3-regulator" - for Pro5 SoC
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"socionext,uniphier-pxs2-usb3-regulator" - for PXs2 SoC
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"socionext,uniphier-ld20-usb3-regulator" - for LD20 SoC
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"socionext,uniphier-pxs3-usb3-regulator" - for PXs3 SoC
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@@ -20,12 +21,12 @@ Required properties:
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- clocks: A list of phandles to the clock gate for USB3 glue layer.
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According to the clock-names, appropriate clocks are required.
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- clock-names: Should contain
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"gio", "link" - for Pro4 SoC
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"gio", "link" - for Pro4 and Pro5 SoCs
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"link" - for others
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- resets: A list of phandles to the reset control for USB3 glue layer.
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According to the reset-names, appropriate resets are required.
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- reset-names: Should contain
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"gio", "link" - for Pro4 SoC
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"gio", "link" - for Pro4 and Pro5 SoCs
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"link" - for others
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See Documentation/devicetree/bindings/regulator/regulator.txt
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