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ANDROID: iommu/io-pgtable-arm: Add IOMMU_CACHE_ICACHE_OCACHE_NWA

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Allow io-coherent devices to use a inner writeback read/write allocate,
outer writeback read allocate, no-write allocate cache policy. The outer
cache policy affects the behavior of a system cache, at least on qcom
boards which have one.

The rational follows that of IOMMU_SYS_CACHE_ONLY_NWA. Certain gpu
usecases perform better when using a no-write allocate policy.

Rename the IOMMU_SYS_CACHE_* flags to better reflect that they are not
exclusive with IOMMU_CACHE.

Bug: 191811876
Change-Id: Ic91616a148f39fead008a5b87a54ffd781fee734
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
This commit is contained in:
Patrick Daly
2021-06-22 12:05:36 -07:00
committed by Will Deacon
parent 2e289f3641
commit 3b6916b4d4
3 changed files with 33 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/iommu/dma-iommu.c
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@@ -434,9 +434,9 @@ static int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
if (attrs & DMA_ATTR_PRIVILEGED) if (attrs & DMA_ATTR_PRIVILEGED)
prot |= IOMMU_PRIV; prot |= IOMMU_PRIV;
if (attrs & DMA_ATTR_SYS_CACHE_ONLY) if (attrs & DMA_ATTR_SYS_CACHE_ONLY)
prot |= IOMMU_SYS_CACHE_ONLY; prot |= IOMMU_SYS_CACHE;
if (attrs & DMA_ATTR_SYS_CACHE_ONLY_NWA) if (attrs & DMA_ATTR_SYS_CACHE_ONLY_NWA)
prot |= IOMMU_SYS_CACHE_ONLY_NWA; prot |= IOMMU_SYS_CACHE_NWA;
switch (dir) { switch (dir) {
case DMA_BIDIRECTIONAL: case DMA_BIDIRECTIONAL:

38
drivers/iommu/io-pgtable-arm.c
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@@ -112,18 +112,20 @@
#define ARM_LPAE_VTCR_PS_SHIFT 16 #define ARM_LPAE_VTCR_PS_SHIFT 16
#define ARM_LPAE_VTCR_PS_MASK 0x7 #define ARM_LPAE_VTCR_PS_MASK 0x7
#define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3) #define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
#define ARM_LPAE_MAIR_ATTR_MASK 0xff #define ARM_LPAE_MAIR_ATTR_MASK 0xff
#define ARM_LPAE_MAIR_ATTR_DEVICE 0x04ULL #define ARM_LPAE_MAIR_ATTR_DEVICE 0x04ULL
#define ARM_LPAE_MAIR_ATTR_NC 0x44ULL #define ARM_LPAE_MAIR_ATTR_NC 0x44ULL
#define ARM_LPAE_MAIR_ATTR_INC_OWBRANWA 0xe4ULL #define ARM_LPAE_MAIR_ATTR_INC_OWBRANWA 0xe4ULL
#define ARM_LPAE_MAIR_ATTR_INC_OWBRWA 0xf4ULL #define ARM_LPAE_MAIR_ATTR_IWBRWA_OWBRANWA 0xefULL
#define ARM_LPAE_MAIR_ATTR_WBRWA 0xffULL #define ARM_LPAE_MAIR_ATTR_INC_OWBRWA 0xf4ULL
#define ARM_LPAE_MAIR_ATTR_IDX_NC 0 #define ARM_LPAE_MAIR_ATTR_WBRWA 0xffULL
#define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1 #define ARM_LPAE_MAIR_ATTR_IDX_NC 0
#define ARM_LPAE_MAIR_ATTR_IDX_DEV 2 #define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
#define ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE 3 #define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
#define ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE_NWA 4 #define ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE 3
#define ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE_NWA 4
#define ARM_LPAE_MAIR_ATTR_IDX_ICACHE_OCACHE_NWA 5
#define ARM_MALI_LPAE_TTBR_ADRMODE_TABLE (3u << 0) #define ARM_MALI_LPAE_TTBR_ADRMODE_TABLE (3u << 0)
#define ARM_MALI_LPAE_TTBR_READ_INNER BIT(2) #define ARM_MALI_LPAE_TTBR_READ_INNER BIT(2)
@@ -435,13 +437,17 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
if (prot & IOMMU_MMIO) if (prot & IOMMU_MMIO)
pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV
<< ARM_LPAE_PTE_ATTRINDX_SHIFT); << ARM_LPAE_PTE_ATTRINDX_SHIFT);
else if ((prot & IOMMU_CACHE) && (prot & IOMMU_SYS_CACHE_NWA))
pte |= (ARM_LPAE_MAIR_ATTR_IDX_ICACHE_OCACHE_NWA
<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
/* IOMMU_CACHE + IOMMU_SYS_CACHE equivalent to IOMMU_CACHE */
else if (prot & IOMMU_CACHE) else if (prot & IOMMU_CACHE)
pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
<< ARM_LPAE_PTE_ATTRINDX_SHIFT); << ARM_LPAE_PTE_ATTRINDX_SHIFT);
else if (prot & IOMMU_SYS_CACHE_ONLY) else if (prot & IOMMU_SYS_CACHE)
pte |= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE pte |= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE
<< ARM_LPAE_PTE_ATTRINDX_SHIFT); << ARM_LPAE_PTE_ATTRINDX_SHIFT);
else if (prot & IOMMU_SYS_CACHE_ONLY_NWA) else if (prot & IOMMU_SYS_CACHE_NWA)
pte |= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE_NWA pte |= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE_NWA
<< ARM_LPAE_PTE_ATTRINDX_SHIFT); << ARM_LPAE_PTE_ATTRINDX_SHIFT);
} }
@@ -904,7 +910,9 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
(ARM_LPAE_MAIR_ATTR_INC_OWBRWA (ARM_LPAE_MAIR_ATTR_INC_OWBRWA
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE)) | << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE)) |
(ARM_LPAE_MAIR_ATTR_INC_OWBRANWA (ARM_LPAE_MAIR_ATTR_INC_OWBRANWA
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE_NWA)); << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE_NWA)) |
(ARM_LPAE_MAIR_ATTR_IWBRWA_OWBRANWA
<< ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_ICACHE_OCACHE_NWA));
cfg->arm_lpae_s1_cfg.mair = reg; cfg->arm_lpae_s1_cfg.mair = reg;

17
include/linux/iommu.h
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@@ -32,18 +32,17 @@
*/ */
#define IOMMU_PRIV (1 << 5) #define IOMMU_PRIV (1 << 5)
/* /*
* Non-coherent masters can use this page protection flag to set cacheable * Allow caching in a transparent outer level of cache, also known as
* memory attributes for only a transparent outer level of cache, also known as * the last-level or system cache, with a read/write allocation policy.
* the last-level or system cache. * Does not depend on IOMMU_CACHE. Incompatible with IOMMU_SYS_CACHE_NWA.
*/ */
#define IOMMU_SYS_CACHE_ONLY (1 << 6) #define IOMMU_SYS_CACHE (1 << 6)
/* /*
* Non-coherent masters can use this page protection flag to set cacheable * Allow caching in a transparent outer level of cache, also known as
* memory attributes with a no write allocation cache policy for only a * the last-level or system cache, with a read allocation policy.
* transparent outer level of cache, also known as the last-level or system * Does not depend on IOMMU_CACHE. Incompatible with IOMMU_SYS_CACHE.
* cache.
*/ */
#define IOMMU_SYS_CACHE_ONLY_NWA (1 << 7) #define IOMMU_SYS_CACHE_NWA (1 << 7)
struct iommu_ops; struct iommu_ops;
struct iommu_group; struct iommu_group;