[PATCH] ARM: 2800/1: OMAP update 3/11: Move OMAP1 core code into mach-omap1 directory
Patch from Tony Lindgren This patch by Paul Mundt and other OMAP developers moves OMAP1 specific IRQ, time, and FPGA code into mach-omap1 directory. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Tony Lindgren
committed by
Russell King
Russell King
parent
b288f75ffa
commit
3b59b6beb4
188
arch/arm/mach-omap1/fpga.c
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188
arch/arm/mach-omap1/fpga.c
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@@ -0,0 +1,188 @@
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/*
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* linux/arch/arm/mach-omap/fpga.c
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*
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* Interrupt handler for OMAP-1510 Innovator FPGA
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*
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* Copyright (C) 2001 RidgeRun, Inc.
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* Author: Greg Lonnon <glonnon@ridgerun.com>
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*
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* Copyright (C) 2002 MontaVista Software, Inc.
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*
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* Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
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* Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/fpga.h>
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#include <asm/arch/gpio.h>
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static void fpga_mask_irq(unsigned int irq)
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{
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irq -= OMAP1510_IH_FPGA_BASE;
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if (irq < 8)
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__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
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& ~(1 << irq)), OMAP1510_FPGA_IMR_LO);
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else if (irq < 16)
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__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
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& ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
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else
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__raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
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& ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
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}
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static inline u32 get_fpga_unmasked_irqs(void)
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{
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return
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((__raw_readb(OMAP1510_FPGA_ISR_LO) &
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__raw_readb(OMAP1510_FPGA_IMR_LO))) |
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((__raw_readb(OMAP1510_FPGA_ISR_HI) &
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__raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) |
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((__raw_readb(INNOVATOR_FPGA_ISR2) &
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__raw_readb(INNOVATOR_FPGA_IMR2)) << 16);
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}
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static void fpga_ack_irq(unsigned int irq)
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{
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/* Don't need to explicitly ACK FPGA interrupts */
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}
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static void fpga_unmask_irq(unsigned int irq)
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{
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irq -= OMAP1510_IH_FPGA_BASE;
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if (irq < 8)
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__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
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OMAP1510_FPGA_IMR_LO);
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else if (irq < 16)
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__raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI)
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| (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI);
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else
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__raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2)
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| (1 << (irq - 16))), INNOVATOR_FPGA_IMR2);
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}
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static void fpga_mask_ack_irq(unsigned int irq)
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{
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fpga_mask_irq(irq);
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fpga_ack_irq(irq);
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}
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void innovator_fpga_IRQ_demux(unsigned int irq, struct irqdesc *desc,
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struct pt_regs *regs)
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{
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struct irqdesc *d;
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u32 stat;
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int fpga_irq;
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stat = get_fpga_unmasked_irqs();
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if (!stat)
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return;
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for (fpga_irq = OMAP1510_IH_FPGA_BASE;
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(fpga_irq < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS)) && stat;
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fpga_irq++, stat >>= 1) {
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if (stat & 1) {
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d = irq_desc + fpga_irq;
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d->handle(fpga_irq, d, regs);
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}
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}
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}
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static struct irqchip omap_fpga_irq_ack = {
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.ack = fpga_mask_ack_irq,
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.mask = fpga_mask_irq,
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.unmask = fpga_unmask_irq,
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};
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static struct irqchip omap_fpga_irq = {
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.ack = fpga_ack_irq,
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.mask = fpga_mask_irq,
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.unmask = fpga_unmask_irq,
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};
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/*
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* All of the FPGA interrupt request inputs except for the touchscreen are
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* edge-sensitive; the touchscreen is level-sensitive. The edge-sensitive
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* interrupts are acknowledged as a side-effect of reading the interrupt
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* status register from the FPGA. The edge-sensitive interrupt inputs
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* cause a problem with level interrupt requests, such as Ethernet. The
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* problem occurs when a level interrupt request is asserted while its
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* interrupt input is masked in the FPGA, which results in a missed
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* interrupt.
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*
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* In an attempt to workaround the problem with missed interrupts, the
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* mask_ack routine for all of the FPGA interrupts has been changed from
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* fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt
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* being serviced is left unmasked. We can do this because the FPGA cascade
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* interrupt is installed with the SA_INTERRUPT flag, which leaves all
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* interrupts masked at the CPU while an FPGA interrupt handler executes.
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*
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* Limited testing indicates that this workaround appears to be effective
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* for the smc9194 Ethernet driver used on the Innovator. It should work
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* on other FPGA interrupts as well, but any drivers that explicitly mask
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* interrupts at the interrupt controller via disable_irq/enable_irq
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* could pose a problem.
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*/
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void omap1510_fpga_init_irq(void)
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{
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int i;
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__raw_writeb(0, OMAP1510_FPGA_IMR_LO);
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__raw_writeb(0, OMAP1510_FPGA_IMR_HI);
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__raw_writeb(0, INNOVATOR_FPGA_IMR2);
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for (i = OMAP1510_IH_FPGA_BASE; i < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS); i++) {
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if (i == OMAP1510_INT_FPGA_TS) {
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/*
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* The touchscreen interrupt is level-sensitive, so
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* we'll use the regular mask_ack routine for it.
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*/
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set_irq_chip(i, &omap_fpga_irq_ack);
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}
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else {
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/*
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* All FPGA interrupts except the touchscreen are
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* edge-sensitive, so we won't mask them.
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*/
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set_irq_chip(i, &omap_fpga_irq);
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}
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set_irq_handler(i, do_edge_IRQ);
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set_irq_flags(i, IRQF_VALID);
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}
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/*
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* The FPGA interrupt line is connected to GPIO13. Claim this pin for
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* the ARM.
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*
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* NOTE: For general GPIO/MPUIO access and interrupts, please see
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* gpio.[ch]
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*/
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omap_request_gpio(13);
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omap_set_gpio_direction(13, 1);
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omap_set_gpio_edge_ctrl(13, OMAP_GPIO_RISING_EDGE);
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set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
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}
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EXPORT_SYMBOL(omap1510_fpga_init_irq);
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234
arch/arm/mach-omap1/irq.c
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234
arch/arm/mach-omap1/irq.c
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@@ -0,0 +1,234 @@
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/*
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* linux/arch/arm/mach-omap/irq.c
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*
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* Interrupt handler for all OMAP boards
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*
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* Copyright (C) 2004 Nokia Corporation
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* Written by Tony Lindgren <tony@atomide.com>
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* Major cleanups by Juha Yrj<72>l<EFBFBD> <juha.yrjola@nokia.com>
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*
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* Completely re-written to support various OMAP chips with bank specific
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* interrupt handlers.
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*
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* Some snippets of the code taken from the older OMAP interrupt handler
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* Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
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*
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* GPIO interrupt handler moved to gpio.c by Juha Yrjola
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/gpio.h>
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#include <asm/io.h>
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#define IRQ_BANK(irq) ((irq) >> 5)
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#define IRQ_BIT(irq) ((irq) & 0x1f)
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struct omap_irq_bank {
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unsigned long base_reg;
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unsigned long trigger_map;
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unsigned long wake_enable;
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};
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static unsigned int irq_bank_count = 0;
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static struct omap_irq_bank *irq_banks;
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static inline unsigned int irq_bank_readl(int bank, int offset)
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{
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return omap_readl(irq_banks[bank].base_reg + offset);
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}
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static inline void irq_bank_writel(unsigned long value, int bank, int offset)
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{
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omap_writel(value, irq_banks[bank].base_reg + offset);
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}
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static void omap_ack_irq(unsigned int irq)
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{
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if (irq > 31)
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omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
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omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
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}
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static void omap_mask_irq(unsigned int irq)
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{
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int bank = IRQ_BANK(irq);
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u32 l;
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l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
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l |= 1 << IRQ_BIT(irq);
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omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
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}
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static void omap_unmask_irq(unsigned int irq)
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{
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int bank = IRQ_BANK(irq);
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u32 l;
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l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
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l &= ~(1 << IRQ_BIT(irq));
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omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
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}
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static void omap_mask_ack_irq(unsigned int irq)
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{
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omap_mask_irq(irq);
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omap_ack_irq(irq);
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}
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static int omap_wake_irq(unsigned int irq, unsigned int enable)
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{
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int bank = IRQ_BANK(irq);
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if (enable)
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irq_banks[bank].wake_enable |= IRQ_BIT(irq);
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else
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irq_banks[bank].wake_enable &= ~IRQ_BIT(irq);
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return 0;
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}
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/*
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* Allows tuning the IRQ type and priority
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*
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* NOTE: There is currently no OMAP fiq handler for Linux. Read the
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* mailing list threads on FIQ handlers if you are planning to
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* add a FIQ handler for OMAP.
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*/
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static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
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{
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signed int bank;
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unsigned long val, offset;
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bank = IRQ_BANK(irq);
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/* FIQ is only available on bank 0 interrupts */
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fiq = bank ? 0 : (fiq & 0x1);
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val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
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offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
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irq_bank_writel(val, bank, offset);
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}
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#ifdef CONFIG_ARCH_OMAP730
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static struct omap_irq_bank omap730_irq_banks[] = {
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{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
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{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
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{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
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};
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#endif
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#ifdef CONFIG_ARCH_OMAP1510
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static struct omap_irq_bank omap1510_irq_banks[] = {
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{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
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{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
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};
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#endif
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#if defined(CONFIG_ARCH_OMAP16XX)
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static struct omap_irq_bank omap1610_irq_banks[] = {
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{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
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{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
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{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
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{ .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
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};
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#endif
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static struct irqchip omap_irq_chip = {
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.ack = omap_mask_ack_irq,
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.mask = omap_mask_irq,
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.unmask = omap_unmask_irq,
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.wake = omap_wake_irq,
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};
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void __init omap_init_irq(void)
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{
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int i, j;
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#ifdef CONFIG_ARCH_OMAP730
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if (cpu_is_omap730()) {
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irq_banks = omap730_irq_banks;
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irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP1510
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if (cpu_is_omap1510()) {
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irq_banks = omap1510_irq_banks;
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irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
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}
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#endif
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#if defined(CONFIG_ARCH_OMAP16XX)
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if (cpu_is_omap16xx()) {
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irq_banks = omap1610_irq_banks;
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irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
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}
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#endif
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printk("Total of %i interrupts in %i interrupt banks\n",
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irq_bank_count * 32, irq_bank_count);
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/* Mask and clear all interrupts */
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for (i = 0; i < irq_bank_count; i++) {
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irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
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irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
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}
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/* Clear any pending interrupts */
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irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
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irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
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/* Enable interrupts in global mask */
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if (cpu_is_omap730()) {
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irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
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}
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/* Install the interrupt handlers for each bank */
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for (i = 0; i < irq_bank_count; i++) {
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for (j = i * 32; j < (i + 1) * 32; j++) {
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int irq_trigger;
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irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
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omap_irq_set_cfg(j, 0, 0, irq_trigger);
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set_irq_chip(j, &omap_irq_chip);
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set_irq_handler(j, do_level_IRQ);
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set_irq_flags(j, IRQF_VALID);
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}
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}
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/* Unmask level 2 handler */
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if (cpu_is_omap730()) {
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omap_unmask_irq(INT_730_IH2_IRQ);
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} else {
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omap_unmask_irq(INT_IH2_IRQ);
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}
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}
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436
arch/arm/mach-omap1/time.c
Normal file
436
arch/arm/mach-omap1/time.c
Normal file
@@ -0,0 +1,436 @@
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/*
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* linux/arch/arm/mach-omap1/time.c
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*
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* OMAP Timers
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*
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* Copyright (C) 2004 Nokia Corporation
|
||||
* Partial timer rewrite and additional dynamic tick timer support by
|
||||
* Tony Lindgen <tony@atomide.com> and
|
||||
* Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
|
||||
*
|
||||
* MPU timer code based on the older MPU timer code for OMAP
|
||||
* Copyright (C) 2000 RidgeRun, Inc.
|
||||
* Author: Greg Lonnon <glonnon@ridgerun.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/leds.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
struct sys_timer omap_timer;
|
||||
|
||||
#ifdef CONFIG_OMAP_MPU_TIMER
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
* MPU timer
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
|
||||
#define OMAP_MPU_TIMER_OFFSET 0x100
|
||||
|
||||
/* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c,
|
||||
* converted to use kHz by Kevin Hilman */
|
||||
/* convert from cycles(64bits) => nanoseconds (64bits)
|
||||
* basic equation:
|
||||
* ns = cycles / (freq / ns_per_sec)
|
||||
* ns = cycles * (ns_per_sec / freq)
|
||||
* ns = cycles * (10^9 / (cpu_khz * 10^3))
|
||||
* ns = cycles * (10^6 / cpu_khz)
|
||||
*
|
||||
* Then we use scaling math (suggested by george at mvista.com) to get:
|
||||
* ns = cycles * (10^6 * SC / cpu_khz / SC
|
||||
* ns = cycles * cyc2ns_scale / SC
|
||||
*
|
||||
* And since SC is a constant power of two, we can convert the div
|
||||
* into a shift.
|
||||
* -johnstul at us.ibm.com "math is hard, lets go shopping!"
|
||||
*/
|
||||
static unsigned long cyc2ns_scale;
|
||||
#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
|
||||
|
||||
static inline void set_cyc2ns_scale(unsigned long cpu_khz)
|
||||
{
|
||||
cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
|
||||
}
|
||||
|
||||
static inline unsigned long long cycles_2_ns(unsigned long long cyc)
|
||||
{
|
||||
return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
|
||||
}
|
||||
|
||||
/*
|
||||
* MPU_TICKS_PER_SEC must be an even number, otherwise machinecycles_to_usecs
|
||||
* will break. On P2, the timer count rate is 6.5 MHz after programming PTV
|
||||
* with 0. This divides the 13MHz input by 2, and is undocumented.
|
||||
*/
|
||||
#ifdef CONFIG_MACH_OMAP_PERSEUS2
|
||||
/* REVISIT: This ifdef construct should be replaced by a query to clock
|
||||
* framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz.
|
||||
*/
|
||||
#define MPU_TICKS_PER_SEC (13000000 / 2)
|
||||
#else
|
||||
#define MPU_TICKS_PER_SEC (12000000 / 2)
|
||||
#endif
|
||||
|
||||
#define MPU_TIMER_TICK_PERIOD ((MPU_TICKS_PER_SEC / HZ) - 1)
|
||||
|
||||
typedef struct {
|
||||
u32 cntl; /* CNTL_TIMER, R/W */
|
||||
u32 load_tim; /* LOAD_TIM, W */
|
||||
u32 read_tim; /* READ_TIM, R */
|
||||
} omap_mpu_timer_regs_t;
|
||||
|
||||
#define omap_mpu_timer_base(n) \
|
||||
((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
|
||||
(n)*OMAP_MPU_TIMER_OFFSET))
|
||||
|
||||
static inline unsigned long omap_mpu_timer_read(int nr)
|
||||
{
|
||||
volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
|
||||
return timer->read_tim;
|
||||
}
|
||||
|
||||
static inline void omap_mpu_timer_start(int nr, unsigned long load_val)
|
||||
{
|
||||
volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
|
||||
|
||||
timer->cntl = MPU_TIMER_CLOCK_ENABLE;
|
||||
udelay(1);
|
||||
timer->load_tim = load_val;
|
||||
udelay(1);
|
||||
timer->cntl = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_AR | MPU_TIMER_ST);
|
||||
}
|
||||
|
||||
unsigned long omap_mpu_timer_ticks_to_usecs(unsigned long nr_ticks)
|
||||
{
|
||||
unsigned long long nsec;
|
||||
|
||||
nsec = cycles_2_ns((unsigned long long)nr_ticks);
|
||||
return (unsigned long)nsec / 1000;
|
||||
}
|
||||
|
||||
/*
|
||||
* Last processed system timer interrupt
|
||||
*/
|
||||
static unsigned long omap_mpu_timer_last = 0;
|
||||
|
||||
/*
|
||||
* Returns elapsed usecs since last system timer interrupt
|
||||
*/
|
||||
static unsigned long omap_mpu_timer_gettimeoffset(void)
|
||||
{
|
||||
unsigned long now = 0 - omap_mpu_timer_read(0);
|
||||
unsigned long elapsed = now - omap_mpu_timer_last;
|
||||
|
||||
return omap_mpu_timer_ticks_to_usecs(elapsed);
|
||||
}
|
||||
|
||||
/*
|
||||
* Elapsed time between interrupts is calculated using timer0.
|
||||
* Latency during the interrupt is calculated using timer1.
|
||||
* Both timer0 and timer1 are counting at 6MHz (P2 6.5MHz).
|
||||
*/
|
||||
static irqreturn_t omap_mpu_timer_interrupt(int irq, void *dev_id,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
unsigned long now, latency;
|
||||
|
||||
write_seqlock(&xtime_lock);
|
||||
now = 0 - omap_mpu_timer_read(0);
|
||||
latency = MPU_TICKS_PER_SEC / HZ - omap_mpu_timer_read(1);
|
||||
omap_mpu_timer_last = now - latency;
|
||||
timer_tick(regs);
|
||||
write_sequnlock(&xtime_lock);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction omap_mpu_timer_irq = {
|
||||
.name = "mpu timer",
|
||||
.flags = SA_INTERRUPT | SA_TIMER,
|
||||
.handler = omap_mpu_timer_interrupt,
|
||||
};
|
||||
|
||||
static unsigned long omap_mpu_timer1_overflows;
|
||||
static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
omap_mpu_timer1_overflows++;
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction omap_mpu_timer1_irq = {
|
||||
.name = "mpu timer1 overflow",
|
||||
.flags = SA_INTERRUPT,
|
||||
.handler = omap_mpu_timer1_interrupt,
|
||||
};
|
||||
|
||||
static __init void omap_init_mpu_timer(void)
|
||||
{
|
||||
set_cyc2ns_scale(MPU_TICKS_PER_SEC / 1000);
|
||||
omap_timer.offset = omap_mpu_timer_gettimeoffset;
|
||||
setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
|
||||
setup_irq(INT_TIMER2, &omap_mpu_timer_irq);
|
||||
omap_mpu_timer_start(0, 0xffffffff);
|
||||
omap_mpu_timer_start(1, MPU_TIMER_TICK_PERIOD);
|
||||
}
|
||||
|
||||
/*
|
||||
* Scheduler clock - returns current time in nanosec units.
|
||||
*/
|
||||
unsigned long long sched_clock(void)
|
||||
{
|
||||
unsigned long ticks = 0 - omap_mpu_timer_read(0);
|
||||
unsigned long long ticks64;
|
||||
|
||||
ticks64 = omap_mpu_timer1_overflows;
|
||||
ticks64 <<= 32;
|
||||
ticks64 |= ticks;
|
||||
|
||||
return cycles_2_ns(ticks64);
|
||||
}
|
||||
#endif /* CONFIG_OMAP_MPU_TIMER */
|
||||
|
||||
#ifdef CONFIG_OMAP_32K_TIMER
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP1510
|
||||
#error OMAP 32KHz timer does not currently work on 1510!
|
||||
#endif
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
* 32KHz OS timer
|
||||
*
|
||||
* This currently works only on 16xx, as 1510 does not have the continuous
|
||||
* 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
|
||||
* of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
|
||||
* on 1510 would be possible, but the timer would not be as accurate as
|
||||
* with the 32KHz synchronized timer.
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
#define OMAP_32K_TIMER_BASE 0xfffb9000
|
||||
#define OMAP_32K_TIMER_CR 0x08
|
||||
#define OMAP_32K_TIMER_TVR 0x00
|
||||
#define OMAP_32K_TIMER_TCR 0x04
|
||||
|
||||
#define OMAP_32K_TICKS_PER_HZ (32768 / HZ)
|
||||
#if (32768 % HZ) != 0
|
||||
/* We cannot ignore modulo.
|
||||
* Potential error can be as high as several percent.
|
||||
*/
|
||||
#define OMAP_32K_TICK_MODULO (32768 % HZ)
|
||||
static unsigned modulo_count = 0; /* Counts 1/HZ units */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
|
||||
* so with HZ = 100, TVR = 327.68.
|
||||
*/
|
||||
#define OMAP_32K_TIMER_TICK_PERIOD ((32768 / HZ) - 1)
|
||||
#define TIMER_32K_SYNCHRONIZED 0xfffbc410
|
||||
|
||||
#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
|
||||
(((nr_jiffies) * (clock_rate)) / HZ)
|
||||
|
||||
static inline void omap_32k_timer_write(int val, int reg)
|
||||
{
|
||||
omap_writew(val, reg + OMAP_32K_TIMER_BASE);
|
||||
}
|
||||
|
||||
static inline unsigned long omap_32k_timer_read(int reg)
|
||||
{
|
||||
return omap_readl(reg + OMAP_32K_TIMER_BASE) & 0xffffff;
|
||||
}
|
||||
|
||||
/*
|
||||
* The 32KHz synchronized timer is an additional timer on 16xx.
|
||||
* It is always running.
|
||||
*/
|
||||
static inline unsigned long omap_32k_sync_timer_read(void)
|
||||
{
|
||||
return omap_readl(TIMER_32K_SYNCHRONIZED);
|
||||
}
|
||||
|
||||
static inline void omap_32k_timer_start(unsigned long load_val)
|
||||
{
|
||||
omap_32k_timer_write(load_val, OMAP_32K_TIMER_TVR);
|
||||
omap_32k_timer_write(0x0f, OMAP_32K_TIMER_CR);
|
||||
}
|
||||
|
||||
static inline void omap_32k_timer_stop(void)
|
||||
{
|
||||
omap_32k_timer_write(0x0, OMAP_32K_TIMER_CR);
|
||||
}
|
||||
|
||||
/*
|
||||
* Rounds down to nearest usec
|
||||
*/
|
||||
static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
|
||||
{
|
||||
return (ticks_32k * 5*5*5*5*5*5) >> 9;
|
||||
}
|
||||
|
||||
static unsigned long omap_32k_last_tick = 0;
|
||||
|
||||
/*
|
||||
* Returns elapsed usecs since last 32k timer interrupt
|
||||
*/
|
||||
static unsigned long omap_32k_timer_gettimeoffset(void)
|
||||
{
|
||||
unsigned long now = omap_32k_sync_timer_read();
|
||||
return omap_32k_ticks_to_usecs(now - omap_32k_last_tick);
|
||||
}
|
||||
|
||||
/*
|
||||
* Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
|
||||
* function is also called from other interrupts to remove latency
|
||||
* issues with dynamic tick. In the dynamic tick case, we need to lock
|
||||
* with irqsave.
|
||||
*/
|
||||
static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
|
||||
struct pt_regs *regs)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long now;
|
||||
|
||||
write_seqlock_irqsave(&xtime_lock, flags);
|
||||
now = omap_32k_sync_timer_read();
|
||||
|
||||
while (now - omap_32k_last_tick >= OMAP_32K_TICKS_PER_HZ) {
|
||||
#ifdef OMAP_32K_TICK_MODULO
|
||||
/* Modulo addition may put omap_32k_last_tick ahead of now
|
||||
* and cause unwanted repetition of the while loop.
|
||||
*/
|
||||
if (unlikely(now - omap_32k_last_tick == ~0))
|
||||
break;
|
||||
|
||||
modulo_count += OMAP_32K_TICK_MODULO;
|
||||
if (modulo_count > HZ) {
|
||||
++omap_32k_last_tick;
|
||||
modulo_count -= HZ;
|
||||
}
|
||||
#endif
|
||||
omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
|
||||
timer_tick(regs);
|
||||
}
|
||||
|
||||
/* Restart timer so we don't drift off due to modulo or dynamic tick.
|
||||
* By default we program the next timer to be continuous to avoid
|
||||
* latencies during high system load. During dynamic tick operation the
|
||||
* continuous timer can be overridden from pm_idle to be longer.
|
||||
*/
|
||||
omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
|
||||
write_sequnlock_irqrestore(&xtime_lock, flags);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NO_IDLE_HZ
|
||||
/*
|
||||
* Programs the next timer interrupt needed. Called when dynamic tick is
|
||||
* enabled, and to reprogram the ticks to skip from pm_idle. Note that
|
||||
* we can keep the timer continuous, and don't need to set it to run in
|
||||
* one-shot mode. This is because the timer will get reprogrammed again
|
||||
* after next interrupt.
|
||||
*/
|
||||
void omap_32k_timer_reprogram(unsigned long next_tick)
|
||||
{
|
||||
omap_32k_timer_start(JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1);
|
||||
}
|
||||
|
||||
static struct irqaction omap_32k_timer_irq;
|
||||
extern struct timer_update_handler timer_update;
|
||||
|
||||
static int omap_32k_timer_enable_dyn_tick(void)
|
||||
{
|
||||
/* No need to reprogram timer, just use the next interrupt */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap_32k_timer_disable_dyn_tick(void)
|
||||
{
|
||||
omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct dyn_tick_timer omap_dyn_tick_timer = {
|
||||
.enable = omap_32k_timer_enable_dyn_tick,
|
||||
.disable = omap_32k_timer_disable_dyn_tick,
|
||||
.reprogram = omap_32k_timer_reprogram,
|
||||
.handler = omap_32k_timer_interrupt,
|
||||
};
|
||||
#endif /* CONFIG_NO_IDLE_HZ */
|
||||
|
||||
static struct irqaction omap_32k_timer_irq = {
|
||||
.name = "32KHz timer",
|
||||
.flags = SA_INTERRUPT | SA_TIMER,
|
||||
.handler = omap_32k_timer_interrupt,
|
||||
};
|
||||
|
||||
static __init void omap_init_32k_timer(void)
|
||||
{
|
||||
|
||||
#ifdef CONFIG_NO_IDLE_HZ
|
||||
omap_timer.dyn_tick = &omap_dyn_tick_timer;
|
||||
#endif
|
||||
|
||||
setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
|
||||
omap_timer.offset = omap_32k_timer_gettimeoffset;
|
||||
omap_32k_last_tick = omap_32k_sync_timer_read();
|
||||
omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
|
||||
}
|
||||
#endif /* CONFIG_OMAP_32K_TIMER */
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
* Timer initialization
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
static void __init omap_timer_init(void)
|
||||
{
|
||||
#if defined(CONFIG_OMAP_MPU_TIMER)
|
||||
omap_init_mpu_timer();
|
||||
#elif defined(CONFIG_OMAP_32K_TIMER)
|
||||
omap_init_32k_timer();
|
||||
#else
|
||||
#error No system timer selected in Kconfig!
|
||||
#endif
|
||||
}
|
||||
|
||||
struct sys_timer omap_timer = {
|
||||
.init = omap_timer_init,
|
||||
.offset = NULL, /* Initialized later */
|
||||
};
|
||||
Reference in New Issue
Block a user