Merge branch 'asoc-5.3' into asoc-5.4
This commit is contained in:
@@ -196,7 +196,7 @@ static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
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{
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u32 bit;
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for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AFSR) {
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for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
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if (enable)
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mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
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else
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@@ -224,6 +224,7 @@ static void mcasp_start_rx(struct davinci_mcasp *mcasp)
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if (mcasp_is_synchronous(mcasp)) {
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
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mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
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mcasp_set_clk_pdir(mcasp, true);
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}
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/* Activate serializer(s) */
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@@ -1263,6 +1264,28 @@ static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
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return ret;
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}
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static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
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struct snd_pcm_hw_rule *rule)
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{
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struct davinci_mcasp_ruledata *rd = rule->private;
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struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
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struct snd_mask nfmt;
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int i, slot_width;
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snd_mask_none(&nfmt);
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slot_width = rd->mcasp->slot_width;
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for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
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if (snd_mask_test(fmt, i)) {
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if (snd_pcm_format_width(i) <= slot_width) {
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snd_mask_set(&nfmt, i);
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}
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}
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}
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return snd_mask_refine(fmt, &nfmt);
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}
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static const unsigned int davinci_mcasp_dai_rates[] = {
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8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
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88200, 96000, 176400, 192000,
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@@ -1384,7 +1407,7 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
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struct davinci_mcasp_ruledata *ruledata =
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&mcasp->ruledata[substream->stream];
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u32 max_channels = 0;
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int i, dir;
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int i, dir, ret;
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int tdm_slots = mcasp->tdm_slots;
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/* Do not allow more then one stream per direction */
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@@ -1413,6 +1436,7 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
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max_channels++;
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}
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ruledata->serializers = max_channels;
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ruledata->mcasp = mcasp;
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max_channels *= tdm_slots;
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/*
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* If the already active stream has less channels than the calculated
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@@ -1439,20 +1463,22 @@ static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
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0, SNDRV_PCM_HW_PARAM_CHANNELS,
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&mcasp->chconstr[substream->stream]);
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if (mcasp->slot_width)
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snd_pcm_hw_constraint_minmax(substream->runtime,
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SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
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8, mcasp->slot_width);
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if (mcasp->slot_width) {
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/* Only allow formats require <= slot_width bits on the bus */
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ret = snd_pcm_hw_rule_add(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_FORMAT,
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davinci_mcasp_hw_rule_slot_width,
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ruledata,
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SNDRV_PCM_HW_PARAM_FORMAT, -1);
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if (ret)
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return ret;
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}
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/*
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* If we rely on implicit BCLK divider setting we should
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* set constraints based on what we can provide.
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*/
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if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
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int ret;
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ruledata->mcasp = mcasp;
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ret = snd_pcm_hw_rule_add(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_RATE,
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davinci_mcasp_hw_rule_rate,
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