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MIPS: Remove unused R6000 support

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The kernel contains a small amount of incomplete code aimed at
supporting old R6000 CPUs. This is:

  - Unused, as no machine selects CONFIG_SYS_HAS_CPU_R6000.

  - Broken, since there are glaring errors such as r6000_fpu.S moving
    the FCSR register to t1, then ignoring it & instead saving t0 into
    struct sigcontext...

  - A maintenance headache, since it's code that nobody can test which
    nevertheless imposes constraints on code which it shares with other
    machines.

Remove this incomplete & broken R6000 CPU support in order to clean up
and in preparation for changes which will no longer need to consider
dragging the pretense of R6000 support along with them.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16236/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
2017-06-05 11:21:27 -07:00
committed by Ralf Baechle
parent 114c370845
commit 3b2db173f0
10 changed files with 3 additions and 165 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/mips/kernel/Makefile
View File

@@ -37,7 +37,6 @@ obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
obj-$(CONFIG_CPU_CAVIUM_OCTEON) += r4k_fpu.o octeon_switch.o

18
arch/mips/kernel/cpu-probe.c
View File

@@ -1394,24 +1394,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
c->tlbsize = 48;
break;
case PRID_IMP_R6000:
c->cputype = CPU_R6000;
__cpu_name[cpu] = "R6000";
set_isa(c, MIPS_CPU_ISA_II);
c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
MIPS_CPU_LLSC;
c->tlbsize = 32;
break;
case PRID_IMP_R6000A:
c->cputype = CPU_R6000A;
__cpu_name[cpu] = "R6000A";
set_isa(c, MIPS_CPU_ISA_II);
c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
MIPS_CPU_LLSC;
c->tlbsize = 32;
break;
case PRID_IMP_RM7000:
c->cputype = CPU_RM7000;
__cpu_name[cpu] = "RM7000";

99
arch/mips/kernel/r6000_fpu.S
View File

@@ -1,99 +0,0 @@
/*
* r6000_fpu.S: Save/restore floating point context for signal handlers.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996 by Ralf Baechle
*
* Multi-arch abstraction and asm macros for easier reading:
* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
*/
#include <asm/asm.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
#include <asm/asm-offsets.h>
#include <asm/regdef.h>
.set noreorder
.set mips2
.set push
SET_HARDFLOAT
/**
* _save_fp_context() - save FP context from the FPU
* @a0 - pointer to fpregs field of sigcontext
* @a1 - pointer to fpc_csr field of sigcontext
*
* Save FP context, including the 32 FP data registers and the FP
* control & status register, from the FPU to signal context.
*/
LEAF(_save_fp_context)
mfc0 t0,CP0_STATUS
sll t0,t0,2
bgez t0,1f
nop
cfc1 t1,fcr31
/* Store the 16 double precision registers */
sdc1 $f0,0(a0)
sdc1 $f2,16(a0)
sdc1 $f4,32(a0)
sdc1 $f6,48(a0)
sdc1 $f8,64(a0)
sdc1 $f10,80(a0)
sdc1 $f12,96(a0)
sdc1 $f14,112(a0)
sdc1 $f16,128(a0)
sdc1 $f18,144(a0)
sdc1 $f20,160(a0)
sdc1 $f22,176(a0)
sdc1 $f24,192(a0)
sdc1 $f26,208(a0)
sdc1 $f28,224(a0)
sdc1 $f30,240(a0)
jr ra
sw t0,(a1)
1: jr ra
nop
END(_save_fp_context)
/**
* _restore_fp_context() - restore FP context to the FPU
* @a0 - pointer to fpregs field of sigcontext
* @a1 - pointer to fpc_csr field of sigcontext
*
* Restore FP context, including the 32 FP data registers and the FP
* control & status register, from signal context to the FPU.
*/
LEAF(_restore_fp_context)
mfc0 t0,CP0_STATUS
sll t0,t0,2
bgez t0,1f
lw t0,(a1)
/* Restore the 16 double precision registers */
ldc1 $f0,0(a0)
ldc1 $f2,16(a0)
ldc1 $f4,32(a0)
ldc1 $f6,48(a0)
ldc1 $f8,64(a0)
ldc1 $f10,80(a0)
ldc1 $f12,96(a0)
ldc1 $f14,112(a0)
ldc1 $f16,128(a0)
ldc1 $f18,144(a0)
ldc1 $f20,160(a0)
ldc1 $f22,176(a0)
ldc1 $f24,192(a0)
ldc1 $f26,208(a0)
ldc1 $f28,224(a0)
ldc1 $f30,240(a0)
jr ra
ctc1 t0,fcr31
1: jr ra
nop
END(_restore_fp_context)
.set pop /* SET_HARDFLOAT */

15
arch/mips/kernel/traps.c
View File

@@ -2428,21 +2428,6 @@ void __init trap_init(void)
set_except_vector(EXCCODE_TR, handle_tr);
set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
if (current_cpu_type() == CPU_R6000 ||
current_cpu_type() == CPU_R6000A) {
/*
* The R6000 is the only R-series CPU that features a machine
* check exception (similar to the R4000 cache error) and
* unaligned ldc1/sdc1 exception. The handlers have not been
* written yet. Well, anyway there is no R6000 machine on the
* current list of targets for Linux/MIPS.
* (Duh, crap, there is someone with a triple R6k machine)
*/
//set_except_vector(14, handle_mc);
//set_except_vector(15, handle_ndc);
}
if (board_nmi_handler_setup)
board_nmi_handler_setup();