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drm/i915: Introduce concept of per-timeline (context) HWSP

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Supplement the per-engine HWSP with a per-timeline HWSP. That is a
per-request pointer through which we can check a local seqno,
abstracting away the presumption of a global seqno. In this first step,
we point each request back into the engine's HWSP so everything
continues to work with the global timeline.

v2: s/i915_request_hwsp/hwsp_seqno/ to emphasis that this is the current
HW value and that we are accessing it via i915_request merely as a
convenience.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190128181812.22804-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
2019-01-28 18:18:07 +00:00
parent 1e345568e3
commit 3adac4689f
3 changed files with 55 additions and 15 deletions
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45
drivers/gpu/drm/i915/i915_request.h
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@@ -130,6 +130,13 @@ struct i915_request {
struct i915_sched_node sched;
struct i915_dependency dep;
/*
* A convenience pointer to the current breadcrumb value stored in
* the HW status page (or our timeline's local equivalent). The full
* path would be rq->hw_context->ring->timeline->hwsp_seqno.
*/
const u32 *hwsp_seqno;
/**
* GEM sequence number associated with this request on the
* global execution timeline. It is zero when the request is not
@@ -285,11 +292,6 @@ static inline bool i915_request_signaled(const struct i915_request *rq)
return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags);
}
static inline bool intel_engine_has_started(struct intel_engine_cs *engine,
u32 seqno);
static inline bool intel_engine_has_completed(struct intel_engine_cs *engine,
u32 seqno);
/**
* Returns true if seq1 is later than seq2.
*/
@@ -298,6 +300,35 @@ static inline bool i915_seqno_passed(u32 seq1, u32 seq2)
return (s32)(seq1 - seq2) >= 0;
}
static inline u32 __hwsp_seqno(const struct i915_request *rq)
{
return READ_ONCE(*rq->hwsp_seqno);
}
/**
* hwsp_seqno - the current breadcrumb value in the HW status page
* @rq: the request, to chase the relevant HW status page
*
* The emphasis in naming here is that hwsp_seqno() is not a property of the
* request, but an indication of the current HW state (associated with this
* request). Its value will change as the GPU executes more requests.
*
* Returns the current breadcrumb value in the associated HW status page (or
* the local timeline's equivalent) for this request. The request itself
* has the associated breadcrumb value of rq->fence.seqno, when the HW
* status page has that breadcrumb or later, this request is complete.
*/
static inline u32 hwsp_seqno(const struct i915_request *rq)
{
u32 seqno;
rcu_read_lock(); /* the HWSP may be freed at runtime */
seqno = __hwsp_seqno(rq);
rcu_read_unlock();
return seqno;
}
/**
* i915_request_started - check if the request has begun being executed
* @rq: the request
@@ -315,14 +346,14 @@ static inline bool i915_request_started(const struct i915_request *rq)
if (!seqno) /* not yet submitted to HW */
return false;
return intel_engine_has_started(rq->engine, seqno);
return i915_seqno_passed(hwsp_seqno(rq), seqno - 1);
}
static inline bool
__i915_request_completed(const struct i915_request *rq, u32 seqno)
{
GEM_BUG_ON(!seqno);
return intel_engine_has_completed(rq->engine, seqno) &&
return i915_seqno_passed(hwsp_seqno(rq), seqno) &&
seqno == i915_request_global_seqno(rq);
}