Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (43 commits) [POWERPC] Use little-endian bit from firmware ibm,pa-features property [POWERPC] Make sure smp_processor_id works very early in boot [POWERPC] U4 DART improvements [POWERPC] todc: add support for Time-Of-Day-Clock [POWERPC] Make lparcfg.c work when both iseries and pseries are selected [POWERPC] Fix idr locking in init_new_context [POWERPC] mpc7448hpc2 (taiga) board config file [POWERPC] Add tsi108 pci and platform device data register function [POWERPC] Add general support for mpc7448hpc2 (Taiga) platform [POWERPC] Correct the MAX_CONTEXT definition powerpc: minor cleanups for mpc86xx [POWERPC] Make sure we select CONFIG_NEW_LEDS if ADB_PMU_LED is set [POWERPC] Simplify the code defining the 64-bit CPU features [POWERPC] powerpc: kconfig warning fix [POWERPC] Consolidate some of kernel/misc*.S [POWERPC] Remove unused function call_with_mmu_off [POWERPC] update asm-powerpc/time.h [POWERPC] Clean up it_lp_queue.h [POWERPC] Skip the "copy down" of the kernel if it is already at zero. [POWERPC] Add the use of the firmware soft-reset-nmi to kdump. ...
此提交包含在：
Linus Torvalds
@@ -12,3 +12,5 @@ obj-$(CONFIG_U3_DART) += dart_iommu.o
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obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
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obj-$(CONFIG_PPC_83xx) += ipic.o
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obj-$(CONFIG_FSL_SOC) += fsl_soc.o
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obj-$(CONFIG_PPC_TODC) += todc.o
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obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
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@@ -47,8 +47,12 @@
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/* U4 registers */
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#define DART_BASE_U4_BASE_MASK 0xffffff
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#define DART_BASE_U4_BASE_SHIFT 0
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#define DART_CNTL_U4_FLUSHTLB 0x20000000
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#define DART_CNTL_U4_ENABLE 0x80000000
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#define DART_CNTL_U4_IONE 0x40000000
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#define DART_CNTL_U4_FLUSHTLB 0x20000000
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#define DART_CNTL_U4_IDLE 0x10000000
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#define DART_CNTL_U4_PAR_EN 0x08000000
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#define DART_CNTL_U4_IONE_MASK 0x07ffffff
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#define DART_SIZE_U4_SIZE_MASK 0x1fff
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#define DART_SIZE_U4_SIZE_SHIFT 0
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@@ -101,8 +101,8 @@ retry:
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if (l == (1L << limit)) {
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if (limit < 4) {
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limit++;
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reg = DART_IN(DART_CNTL);
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reg &= ~inv_bit;
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reg = DART_IN(DART_CNTL);
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reg &= ~inv_bit;
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DART_OUT(DART_CNTL, reg);
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goto retry;
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} else
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@@ -111,11 +111,39 @@ retry:
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}
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}
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static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
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{
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unsigned int reg;
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unsigned int l, limit;
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reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
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(bus_rpn & DART_CNTL_U4_IONE_MASK);
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DART_OUT(DART_CNTL, reg);
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limit = 0;
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wait_more:
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l = 0;
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while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) {
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rmb();
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l++;
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}
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if (l == (1L << limit)) {
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if (limit < 4) {
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limit++;
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goto wait_more;
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} else
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panic("DART: TLB did not flush after waiting a long "
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"time. Buggy U4 ?");
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}
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}
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static void dart_flush(struct iommu_table *tbl)
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{
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if (dart_dirty)
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if (dart_dirty) {
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dart_tlb_invalidate_all();
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dart_dirty = 0;
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dart_dirty = 0;
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}
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}
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static void dart_build(struct iommu_table *tbl, long index,
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@@ -124,6 +152,7 @@ static void dart_build(struct iommu_table *tbl, long index,
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{
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unsigned int *dp;
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unsigned int rpn;
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long l;
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DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
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@@ -135,7 +164,8 @@ static void dart_build(struct iommu_table *tbl, long index,
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/* On U3, all memory is contigous, so we can move this
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* out of the loop.
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*/
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while (npages--) {
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l = npages;
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while (l--) {
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rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT;
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*(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
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@@ -143,7 +173,14 @@ static void dart_build(struct iommu_table *tbl, long index,
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uaddr += DART_PAGE_SIZE;
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}
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dart_dirty = 1;
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if (dart_is_u4) {
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rpn = index;
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mb(); /* make sure all updates have reached memory */
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while (npages--)
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dart_tlb_invalidate_one(rpn++);
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} else {
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dart_dirty = 1;
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}
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}
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392
arch/powerpc/sysdev/todc.c
一般檔案
392
arch/powerpc/sysdev/todc.c
一般檔案
@@ -0,0 +1,392 @@
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/*
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* Time of Day Clock support for the M48T35, M48T37, M48T59, and MC146818
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* Real Time Clocks/Timekeepers.
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*
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* Author: Mark A. Greer <mgreer@mvista.com>
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*
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* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/bcd.h>
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#include <linux/mc146818rtc.h>
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#include <asm/machdep.h>
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#include <asm/io.h>
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#include <asm/time.h>
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#include <asm/todc.h>
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/*
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* Depending on the hardware on your board and your board design, the
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* RTC/NVRAM may be accessed either directly (like normal memory) or via
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* address/data registers. If your board uses the direct method, set
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* 'nvram_data' to the base address of your nvram and leave 'nvram_as0' and
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* 'nvram_as1' NULL. If your board uses address/data regs to access nvram,
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* set 'nvram_as0' to the address of the lower byte, set 'nvram_as1' to the
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* address of the upper byte (leave NULL if using mc146818), and set
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* 'nvram_data' to the address of the 8-bit data register.
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*
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* Note: Even though the documentation for the various RTC chips say that it
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* take up to a second before it starts updating once the 'R' bit is
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* cleared, they always seem to update even though we bang on it many
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* times a second. This is true, except for the Dallas Semi 1746/1747
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* (possibly others). Those chips seem to have a real problem whenever
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* we set the 'R' bit before reading them, they basically stop counting.
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* --MAG
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*/
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/*
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* 'todc_info' should be initialized in your *_setup.c file to
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* point to a fully initialized 'todc_info_t' structure.
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* This structure holds all the register offsets for your particular
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* TODC/RTC chip.
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* TODC_ALLOC()/TODC_INIT() will allocate and initialize this table for you.
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*/
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#ifdef RTC_FREQ_SELECT
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#undef RTC_FREQ_SELECT
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#define RTC_FREQ_SELECT control_b /* Register A */
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#endif
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#ifdef RTC_CONTROL
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#undef RTC_CONTROL
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#define RTC_CONTROL control_a /* Register B */
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#endif
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#ifdef RTC_INTR_FLAGS
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#undef RTC_INTR_FLAGS
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#define RTC_INTR_FLAGS watchdog /* Register C */
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#endif
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#ifdef RTC_VALID
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#undef RTC_VALID
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#define RTC_VALID interrupts /* Register D */
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#endif
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/* Access routines when RTC accessed directly (like normal memory) */
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u_char
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todc_direct_read_val(int addr)
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{
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return readb((void __iomem *)(todc_info->nvram_data + addr));
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}
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void
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todc_direct_write_val(int addr, unsigned char val)
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{
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writeb(val, (void __iomem *)(todc_info->nvram_data + addr));
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return;
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}
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/* Access routines for accessing m48txx type chips via addr/data regs */
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u_char
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todc_m48txx_read_val(int addr)
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{
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outb(addr, todc_info->nvram_as0);
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outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
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return inb(todc_info->nvram_data);
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}
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void
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todc_m48txx_write_val(int addr, unsigned char val)
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{
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outb(addr, todc_info->nvram_as0);
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outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
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outb(val, todc_info->nvram_data);
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return;
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}
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/* Access routines for accessing mc146818 type chips via addr/data regs */
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u_char
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todc_mc146818_read_val(int addr)
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{
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outb_p(addr, todc_info->nvram_as0);
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return inb_p(todc_info->nvram_data);
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}
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void
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todc_mc146818_write_val(int addr, unsigned char val)
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{
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outb_p(addr, todc_info->nvram_as0);
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outb_p(val, todc_info->nvram_data);
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}
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/*
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* Routines to make RTC chips with NVRAM buried behind an addr/data pair
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* have the NVRAM and clock regs appear at the same level.
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* The NVRAM will appear to start at addr 0 and the clock regs will appear
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* to start immediately after the NVRAM (actually, start at offset
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* todc_info->nvram_size).
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*/
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static inline u_char
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todc_read_val(int addr)
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{
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u_char val;
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if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
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if (addr < todc_info->nvram_size) { /* NVRAM */
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ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
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val = ppc_md.rtc_read_val(todc_info->nvram_data_reg);
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} else { /* Clock Reg */
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addr -= todc_info->nvram_size;
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val = ppc_md.rtc_read_val(addr);
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}
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} else
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val = ppc_md.rtc_read_val(addr);
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return val;
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}
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static inline void
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todc_write_val(int addr, u_char val)
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{
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if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
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if (addr < todc_info->nvram_size) { /* NVRAM */
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ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
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ppc_md.rtc_write_val(todc_info->nvram_data_reg, val);
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} else { /* Clock Reg */
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||||
addr -= todc_info->nvram_size;
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ppc_md.rtc_write_val(addr, val);
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}
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||||
} else
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ppc_md.rtc_write_val(addr, val);
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||||
}
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||||
|
||||
/*
|
||||
* TODC routines
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||||
*
|
||||
* There is some ugly stuff in that there are assumptions for the mc146818.
|
||||
*
|
||||
* Assumptions:
|
||||
* - todc_info->control_a has the offset as mc146818 Register B reg
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||||
* - todc_info->control_b has the offset as mc146818 Register A reg
|
||||
* - m48txx control reg's write enable or 'W' bit is same as
|
||||
* mc146818 Register B 'SET' bit (i.e., 0x80)
|
||||
*
|
||||
* These assumptions were made to make the code simpler.
|
||||
*/
|
||||
long __init
|
||||
todc_time_init(void)
|
||||
{
|
||||
u_char cntl_b;
|
||||
|
||||
if (!ppc_md.rtc_read_val)
|
||||
ppc_md.rtc_read_val = ppc_md.nvram_read_val;
|
||||
if (!ppc_md.rtc_write_val)
|
||||
ppc_md.rtc_write_val = ppc_md.nvram_write_val;
|
||||
|
||||
cntl_b = todc_read_val(todc_info->control_b);
|
||||
|
||||
if (todc_info->rtc_type == TODC_TYPE_MC146818) {
|
||||
if ((cntl_b & 0x70) != 0x20) {
|
||||
printk(KERN_INFO "TODC real-time-clock was stopped."
|
||||
" Now starting...");
|
||||
cntl_b &= ~0x70;
|
||||
cntl_b |= 0x20;
|
||||
}
|
||||
|
||||
todc_write_val(todc_info->control_b, cntl_b);
|
||||
} else if (todc_info->rtc_type == TODC_TYPE_DS17285) {
|
||||
u_char mode;
|
||||
|
||||
mode = todc_read_val(TODC_TYPE_DS17285_CNTL_A);
|
||||
/* Make sure countdown clear is not set */
|
||||
mode &= ~0x40;
|
||||
/* Enable oscillator, extended register set */
|
||||
mode |= 0x30;
|
||||
todc_write_val(TODC_TYPE_DS17285_CNTL_A, mode);
|
||||
|
||||
} else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
|
||||
u_char month;
|
||||
|
||||
todc_info->enable_read = TODC_DS1501_CNTL_B_TE;
|
||||
todc_info->enable_write = TODC_DS1501_CNTL_B_TE;
|
||||
|
||||
month = todc_read_val(todc_info->month);
|
||||
|
||||
if ((month & 0x80) == 0x80) {
|
||||
printk(KERN_INFO "TODC %s %s\n",
|
||||
"real-time-clock was stopped.",
|
||||
"Now starting...");
|
||||
month &= ~0x80;
|
||||
todc_write_val(todc_info->month, month);
|
||||
}
|
||||
|
||||
cntl_b &= ~TODC_DS1501_CNTL_B_TE;
|
||||
todc_write_val(todc_info->control_b, cntl_b);
|
||||
} else { /* must be a m48txx type */
|
||||
u_char cntl_a;
|
||||
|
||||
todc_info->enable_read = TODC_MK48TXX_CNTL_A_R;
|
||||
todc_info->enable_write = TODC_MK48TXX_CNTL_A_W;
|
||||
|
||||
cntl_a = todc_read_val(todc_info->control_a);
|
||||
|
||||
/* Check & clear STOP bit in control B register */
|
||||
if (cntl_b & TODC_MK48TXX_DAY_CB) {
|
||||
printk(KERN_INFO "TODC %s %s\n",
|
||||
"real-time-clock was stopped.",
|
||||
"Now starting...");
|
||||
|
||||
cntl_a |= todc_info->enable_write;
|
||||
cntl_b &= ~TODC_MK48TXX_DAY_CB;/* Start Oscil */
|
||||
|
||||
todc_write_val(todc_info->control_a, cntl_a);
|
||||
todc_write_val(todc_info->control_b, cntl_b);
|
||||
}
|
||||
|
||||
/* Make sure READ & WRITE bits are cleared. */
|
||||
cntl_a &= ~(todc_info->enable_write | todc_info->enable_read);
|
||||
todc_write_val(todc_info->control_a, cntl_a);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* There is some ugly stuff in that there are assumptions that for a mc146818,
|
||||
* the todc_info->control_a has the offset of the mc146818 Register B reg and
|
||||
* that the register'ss 'SET' bit is the same as the m48txx's write enable
|
||||
* bit in the control register of the m48txx (i.e., 0x80).
|
||||
*
|
||||
* It was done to make the code look simpler.
|
||||
*/
|
||||
void
|
||||
todc_get_rtc_time(struct rtc_time *tm)
|
||||
{
|
||||
uint year = 0, mon = 0, mday = 0, hour = 0, min = 0, sec = 0;
|
||||
uint limit, i;
|
||||
u_char save_control, uip = 0;
|
||||
extern void GregorianDay(struct rtc_time *);
|
||||
|
||||
spin_lock(&rtc_lock);
|
||||
save_control = todc_read_val(todc_info->control_a);
|
||||
|
||||
if (todc_info->rtc_type != TODC_TYPE_MC146818) {
|
||||
limit = 1;
|
||||
|
||||
switch (todc_info->rtc_type) {
|
||||
case TODC_TYPE_DS1553:
|
||||
case TODC_TYPE_DS1557:
|
||||
case TODC_TYPE_DS1743:
|
||||
case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
|
||||
case TODC_TYPE_DS1747:
|
||||
case TODC_TYPE_DS17285:
|
||||
break;
|
||||
default:
|
||||
todc_write_val(todc_info->control_a,
|
||||
(save_control | todc_info->enable_read));
|
||||
}
|
||||
} else
|
||||
limit = 100000000;
|
||||
|
||||
for (i=0; i<limit; i++) {
|
||||
if (todc_info->rtc_type == TODC_TYPE_MC146818)
|
||||
uip = todc_read_val(todc_info->RTC_FREQ_SELECT);
|
||||
|
||||
sec = todc_read_val(todc_info->seconds) & 0x7f;
|
||||
min = todc_read_val(todc_info->minutes) & 0x7f;
|
||||
hour = todc_read_val(todc_info->hours) & 0x3f;
|
||||
mday = todc_read_val(todc_info->day_of_month) & 0x3f;
|
||||
mon = todc_read_val(todc_info->month) & 0x1f;
|
||||
year = todc_read_val(todc_info->year) & 0xff;
|
||||
|
||||
if (todc_info->rtc_type == TODC_TYPE_MC146818) {
|
||||
uip |= todc_read_val(todc_info->RTC_FREQ_SELECT);
|
||||
if ((uip & RTC_UIP) == 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (todc_info->rtc_type != TODC_TYPE_MC146818) {
|
||||
switch (todc_info->rtc_type) {
|
||||
case TODC_TYPE_DS1553:
|
||||
case TODC_TYPE_DS1557:
|
||||
case TODC_TYPE_DS1743:
|
||||
case TODC_TYPE_DS1746: /* XXXX BAD HACK -> FIX */
|
||||
case TODC_TYPE_DS1747:
|
||||
case TODC_TYPE_DS17285:
|
||||
break;
|
||||
default:
|
||||
save_control &= ~(todc_info->enable_read);
|
||||
todc_write_val(todc_info->control_a, save_control);
|
||||
}
|
||||
}
|
||||
spin_unlock(&rtc_lock);
|
||||
|
||||
if ((todc_info->rtc_type != TODC_TYPE_MC146818)
|
||||
|| ((save_control & RTC_DM_BINARY) == 0)
|
||||
|| RTC_ALWAYS_BCD) {
|
||||
BCD_TO_BIN(sec);
|
||||
BCD_TO_BIN(min);
|
||||
BCD_TO_BIN(hour);
|
||||
BCD_TO_BIN(mday);
|
||||
BCD_TO_BIN(mon);
|
||||
BCD_TO_BIN(year);
|
||||
}
|
||||
|
||||
if ((year + 1900) < 1970) {
|
||||
year += 100;
|
||||
}
|
||||
|
||||
tm->tm_sec = sec;
|
||||
tm->tm_min = min;
|
||||
tm->tm_hour = hour;
|
||||
tm->tm_mday = mday;
|
||||
tm->tm_mon = mon;
|
||||
tm->tm_year = year;
|
||||
|
||||
GregorianDay(tm);
|
||||
}
|
||||
|
||||
int
|
||||
todc_set_rtc_time(struct rtc_time *tm)
|
||||
{
|
||||
u_char save_control, save_freq_select = 0;
|
||||
|
||||
spin_lock(&rtc_lock);
|
||||
save_control = todc_read_val(todc_info->control_a);
|
||||
|
||||
/* Assuming MK48T59_RTC_CA_WRITE & RTC_SET are equal */
|
||||
todc_write_val(todc_info->control_a,
|
||||
(save_control | todc_info->enable_write));
|
||||
save_control &= ~(todc_info->enable_write); /* in case it was set */
|
||||
|
||||
if (todc_info->rtc_type == TODC_TYPE_MC146818) {
|
||||
save_freq_select = todc_read_val(todc_info->RTC_FREQ_SELECT);
|
||||
todc_write_val(todc_info->RTC_FREQ_SELECT,
|
||||
save_freq_select | RTC_DIV_RESET2);
|
||||
}
|
||||
|
||||
if ((todc_info->rtc_type != TODC_TYPE_MC146818)
|
||||
|| ((save_control & RTC_DM_BINARY) == 0)
|
||||
|| RTC_ALWAYS_BCD) {
|
||||
BIN_TO_BCD(tm->tm_sec);
|
||||
BIN_TO_BCD(tm->tm_min);
|
||||
BIN_TO_BCD(tm->tm_hour);
|
||||
BIN_TO_BCD(tm->tm_mon);
|
||||
BIN_TO_BCD(tm->tm_mday);
|
||||
BIN_TO_BCD(tm->tm_year);
|
||||
}
|
||||
|
||||
todc_write_val(todc_info->seconds, tm->tm_sec);
|
||||
todc_write_val(todc_info->minutes, tm->tm_min);
|
||||
todc_write_val(todc_info->hours, tm->tm_hour);
|
||||
todc_write_val(todc_info->month, tm->tm_mon);
|
||||
todc_write_val(todc_info->day_of_month, tm->tm_mday);
|
||||
todc_write_val(todc_info->year, tm->tm_year);
|
||||
|
||||
todc_write_val(todc_info->control_a, save_control);
|
||||
|
||||
if (todc_info->rtc_type == TODC_TYPE_MC146818)
|
||||
todc_write_val(todc_info->RTC_FREQ_SELECT, save_freq_select);
|
||||
|
||||
spin_unlock(&rtc_lock);
|
||||
return 0;
|
||||
}
|
||||
145
arch/powerpc/sysdev/tsi108_dev.c
一般檔案
145
arch/powerpc/sysdev/tsi108_dev.c
一般檔案
@@ -0,0 +1,145 @@
|
||||
/*
|
||||
* tsi108/109 device setup code
|
||||
*
|
||||
* Maintained by Roy Zang < tie-fei.zang@freescale.com >
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/config.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/major.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <asm/tsi108.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/atomic.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/prom.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DBG(fmt...) do { printk(fmt); } while(0)
|
||||
#else
|
||||
#define DBG(fmt...) do { } while(0)
|
||||
#endif
|
||||
|
||||
static phys_addr_t tsi108_csr_base = -1;
|
||||
|
||||
phys_addr_t get_csrbase(void)
|
||||
{
|
||||
struct device_node *tsi;
|
||||
|
||||
if (tsi108_csr_base != -1)
|
||||
return tsi108_csr_base;
|
||||
|
||||
tsi = of_find_node_by_type(NULL, "tsi-bridge");
|
||||
if (tsi) {
|
||||
unsigned int size;
|
||||
void *prop = get_property(tsi, "reg", &size);
|
||||
tsi108_csr_base = of_translate_address(tsi, prop);
|
||||
of_node_put(tsi);
|
||||
};
|
||||
return tsi108_csr_base;
|
||||
}
|
||||
|
||||
u32 get_vir_csrbase(void)
|
||||
{
|
||||
return (u32) (ioremap(get_csrbase(), 0x10000));
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(get_csrbase);
|
||||
EXPORT_SYMBOL(get_vir_csrbase);
|
||||
|
||||
static int __init tsi108_eth_of_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
unsigned int i;
|
||||
struct platform_device *tsi_eth_dev;
|
||||
struct resource res;
|
||||
int ret;
|
||||
|
||||
for (np = NULL, i = 0;
|
||||
(np = of_find_compatible_node(np, "network", "tsi-ethernet")) != NULL;
|
||||
i++) {
|
||||
struct resource r[2];
|
||||
struct device_node *phy;
|
||||
hw_info tsi_eth_data;
|
||||
unsigned int *id;
|
||||
unsigned int *phy_id;
|
||||
void *mac_addr;
|
||||
phandle *ph;
|
||||
|
||||
memset(r, 0, sizeof(r));
|
||||
memset(&tsi_eth_data, 0, sizeof(tsi_eth_data));
|
||||
|
||||
ret = of_address_to_resource(np, 0, &r[0]);
|
||||
DBG("%s: name:start->end = %s:0x%lx-> 0x%lx\n",
|
||||
__FUNCTION__,r[0].name, r[0].start, r[0].end);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
r[1].name = "tx";
|
||||
r[1].start = np->intrs[0].line;
|
||||
r[1].end = np->intrs[0].line;
|
||||
r[1].flags = IORESOURCE_IRQ;
|
||||
|
||||
tsi_eth_dev =
|
||||
platform_device_register_simple("tsi-ethernet", i, &r[0],
|
||||
np->n_intrs + 1);
|
||||
|
||||
if (IS_ERR(tsi_eth_dev)) {
|
||||
ret = PTR_ERR(tsi_eth_dev);
|
||||
goto err;
|
||||
}
|
||||
|
||||
mac_addr = get_property(np, "address", NULL);
|
||||
memcpy(tsi_eth_data.mac_addr, mac_addr, 6);
|
||||
|
||||
ph = (phandle *) get_property(np, "phy-handle", NULL);
|
||||
phy = of_find_node_by_phandle(*ph);
|
||||
|
||||
if (phy == NULL) {
|
||||
ret = -ENODEV;
|
||||
goto unreg;
|
||||
}
|
||||
|
||||
id = (u32 *) get_property(phy, "reg", NULL);
|
||||
phy_id = (u32 *) get_property(phy, "phy-id", NULL);
|
||||
ret = of_address_to_resource(phy, 0, &res);
|
||||
if (ret) {
|
||||
of_node_put(phy);
|
||||
goto unreg;
|
||||
}
|
||||
tsi_eth_data.regs = r[0].start;
|
||||
tsi_eth_data.phyregs = res.start;
|
||||
tsi_eth_data.phy = *phy_id;
|
||||
tsi_eth_data.irq_num = np->intrs[0].line;
|
||||
of_node_put(phy);
|
||||
ret =
|
||||
platform_device_add_data(tsi_eth_dev, &tsi_eth_data,
|
||||
sizeof(hw_info));
|
||||
if (ret)
|
||||
goto unreg;
|
||||
}
|
||||
return 0;
|
||||
unreg:
|
||||
platform_device_unregister(tsi_eth_dev);
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
arch_initcall(tsi108_eth_of_init);
|
||||
412
arch/powerpc/sysdev/tsi108_pci.c
一般檔案
412
arch/powerpc/sysdev/tsi108_pci.c
一般檔案
@@ -0,0 +1,412 @@
|
||||
/*
|
||||
* Common routines for Tundra Semiconductor TSI108 host bridge.
|
||||
*
|
||||
* 2004-2005 (c) Tundra Semiconductor Corp.
|
||||
* Author: Alex Bounine (alexandreb@tundra.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the Free
|
||||
* Software Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/tsi108.h>
|
||||
#include <asm/tsi108_irq.h>
|
||||
#include <asm/prom.h>
|
||||
|
||||
#undef DEBUG
|
||||
#ifdef DEBUG
|
||||
#define DBG(x...) printk(x)
|
||||
#else
|
||||
#define DBG(x...)
|
||||
#endif
|
||||
|
||||
#define tsi_mk_config_addr(bus, devfunc, offset) \
|
||||
((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base)
|
||||
|
||||
u32 tsi108_pci_cfg_base;
|
||||
u32 tsi108_csr_vir_base;
|
||||
|
||||
extern u32 get_vir_csrbase(void);
|
||||
extern u32 tsi108_read_reg(u32 reg_offset);
|
||||
extern void tsi108_write_reg(u32 reg_offset, u32 val);
|
||||
|
||||
int
|
||||
tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
|
||||
int offset, int len, u32 val)
|
||||
{
|
||||
volatile unsigned char *cfg_addr;
|
||||
|
||||
if (ppc_md.pci_exclude_device)
|
||||
if (ppc_md.pci_exclude_device(bus->number, devfunc))
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
|
||||
devfunc, offset) |
|
||||
(offset & 0x03));
|
||||
|
||||
#ifdef DEBUG
|
||||
printk("PCI CFG write : ");
|
||||
printk("%d:0x%x:0x%x ", bus->number, devfunc, offset);
|
||||
printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
|
||||
printk("data = 0x%08x\n", val);
|
||||
#endif
|
||||
|
||||
switch (len) {
|
||||
case 1:
|
||||
out_8((u8 *) cfg_addr, val);
|
||||
break;
|
||||
case 2:
|
||||
out_le16((u16 *) cfg_addr, val);
|
||||
break;
|
||||
default:
|
||||
out_le32((u32 *) cfg_addr, val);
|
||||
break;
|
||||
}
|
||||
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
void tsi108_clear_pci_error(u32 pci_cfg_base)
|
||||
{
|
||||
u32 err_stat, err_addr, pci_stat;
|
||||
|
||||
/*
|
||||
* Quietly clear PB and PCI error flags set as result
|
||||
* of PCI/X configuration read requests.
|
||||
*/
|
||||
|
||||
/* Read PB Error Log Registers */
|
||||
|
||||
err_stat = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS);
|
||||
err_addr = tsi108_read_reg(TSI108_PB_OFFSET + TSI108_PB_AERR);
|
||||
|
||||
if (err_stat & TSI108_PB_ERRCS_ES) {
|
||||
/* Clear error flag */
|
||||
tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ERRCS,
|
||||
TSI108_PB_ERRCS_ES);
|
||||
|
||||
/* Clear read error reported in PB_ISR */
|
||||
tsi108_write_reg(TSI108_PB_OFFSET + TSI108_PB_ISR,
|
||||
TSI108_PB_ISR_PBS_RD_ERR);
|
||||
|
||||
/* Clear PCI/X bus cfg errors if applicable */
|
||||
if ((err_addr & 0xFF000000) == pci_cfg_base) {
|
||||
pci_stat =
|
||||
tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR);
|
||||
tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_CSR,
|
||||
pci_stat);
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#define __tsi108_read_pci_config(x, addr, op) \
|
||||
__asm__ __volatile__( \
|
||||
" "op" %0,0,%1\n" \
|
||||
"1: eieio\n" \
|
||||
"2:\n" \
|
||||
".section .fixup,\"ax\"\n" \
|
||||
"3: li %0,-1\n" \
|
||||
" b 2b\n" \
|
||||
".section __ex_table,\"a\"\n" \
|
||||
" .align 2\n" \
|
||||
" .long 1b,3b\n" \
|
||||
".text" \
|
||||
: "=r"(x) : "r"(addr))
|
||||
|
||||
int
|
||||
tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
|
||||
int len, u32 * val)
|
||||
{
|
||||
volatile unsigned char *cfg_addr;
|
||||
u32 temp;
|
||||
|
||||
if (ppc_md.pci_exclude_device)
|
||||
if (ppc_md.pci_exclude_device(bus->number, devfn))
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
cfg_addr = (unsigned char *)(tsi_mk_config_addr(bus->number,
|
||||
devfn,
|
||||
offset) | (offset &
|
||||
0x03));
|
||||
|
||||
switch (len) {
|
||||
case 1:
|
||||
__tsi108_read_pci_config(temp, cfg_addr, "lbzx");
|
||||
break;
|
||||
case 2:
|
||||
__tsi108_read_pci_config(temp, cfg_addr, "lhbrx");
|
||||
break;
|
||||
default:
|
||||
__tsi108_read_pci_config(temp, cfg_addr, "lwbrx");
|
||||
break;
|
||||
}
|
||||
|
||||
*val = temp;
|
||||
|
||||
#ifdef DEBUG
|
||||
if ((0xFFFFFFFF != temp) && (0xFFFF != temp) && (0xFF != temp)) {
|
||||
printk("PCI CFG read : ");
|
||||
printk("%d:0x%x:0x%x ", bus->number, devfn, offset);
|
||||
printk("%d ADDR=0x%08x ", len, (uint) cfg_addr);
|
||||
printk("data = 0x%x\n", *val);
|
||||
}
|
||||
#endif
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
void tsi108_clear_pci_cfg_error(void)
|
||||
{
|
||||
tsi108_clear_pci_error(TSI108_PCI_CFG_BASE_PHYS);
|
||||
}
|
||||
|
||||
static struct pci_ops tsi108_direct_pci_ops = {
|
||||
tsi108_direct_read_config,
|
||||
tsi108_direct_write_config
|
||||
};
|
||||
|
||||
int __init tsi108_setup_pci(struct device_node *dev)
|
||||
{
|
||||
int len;
|
||||
struct pci_controller *hose;
|
||||
struct resource rsrc;
|
||||
int *bus_range;
|
||||
int primary = 0, has_address = 0;
|
||||
|
||||
/* PCI Config mapping */
|
||||
tsi108_pci_cfg_base = (u32)ioremap(TSI108_PCI_CFG_BASE_PHYS,
|
||||
TSI108_PCI_CFG_SIZE);
|
||||
DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
|
||||
tsi108_pci_cfg_base);
|
||||
|
||||
/* Fetch host bridge registers address */
|
||||
has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
|
||||
|
||||
/* Get bus range if any */
|
||||
bus_range = (int *)get_property(dev, "bus-range", &len);
|
||||
if (bus_range == NULL || len < 2 * sizeof(int)) {
|
||||
printk(KERN_WARNING "Can't get bus-range for %s, assume"
|
||||
" bus 0\n", dev->full_name);
|
||||
}
|
||||
|
||||
hose = pcibios_alloc_controller();
|
||||
|
||||
if (!hose) {
|
||||
printk("PCI Host bridge init failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
hose->arch_data = dev;
|
||||
hose->set_cfg_type = 1;
|
||||
|
||||
hose->first_busno = bus_range ? bus_range[0] : 0;
|
||||
hose->last_busno = bus_range ? bus_range[1] : 0xff;
|
||||
|
||||
(hose)->ops = &tsi108_direct_pci_ops;
|
||||
|
||||
printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08lx. "
|
||||
"Firmware bus number: %d->%d\n",
|
||||
rsrc.start, hose->first_busno, hose->last_busno);
|
||||
|
||||
/* Interpret the "ranges" property */
|
||||
/* This also maps the I/O region and sets isa_io/mem_base */
|
||||
pci_process_bridge_OF_ranges(hose, dev, primary);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Low level utility functions
|
||||
*/
|
||||
|
||||
static void tsi108_pci_int_mask(u_int irq)
|
||||
{
|
||||
u_int irp_cfg;
|
||||
int int_line = (irq - IRQ_PCI_INTAD_BASE);
|
||||
|
||||
irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
|
||||
mb();
|
||||
irp_cfg |= (1 << int_line); /* INTx_DIR = output */
|
||||
irp_cfg &= ~(3 << (8 + (int_line * 2))); /* INTx_TYPE = unused */
|
||||
tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
|
||||
mb();
|
||||
irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
|
||||
}
|
||||
|
||||
static void tsi108_pci_int_unmask(u_int irq)
|
||||
{
|
||||
u_int irp_cfg;
|
||||
int int_line = (irq - IRQ_PCI_INTAD_BASE);
|
||||
|
||||
irp_cfg = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
|
||||
mb();
|
||||
irp_cfg &= ~(1 << int_line);
|
||||
irp_cfg |= (3 << (8 + (int_line * 2)));
|
||||
tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL, irp_cfg);
|
||||
mb();
|
||||
}
|
||||
|
||||
static void init_pci_source(void)
|
||||
{
|
||||
tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL,
|
||||
0x0000ff00);
|
||||
tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
|
||||
TSI108_PCI_IRP_ENABLE_P_INT);
|
||||
mb();
|
||||
}
|
||||
|
||||
static inline int get_pci_source(void)
|
||||
{
|
||||
u_int temp = 0;
|
||||
int irq = -1;
|
||||
int i;
|
||||
u_int pci_irp_stat;
|
||||
static int mask = 0;
|
||||
|
||||
/* Read PCI/X block interrupt status register */
|
||||
pci_irp_stat = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
|
||||
mb();
|
||||
|
||||
if (pci_irp_stat & TSI108_PCI_IRP_STAT_P_INT) {
|
||||
/* Process Interrupt from PCI bus INTA# - INTD# lines */
|
||||
temp =
|
||||
tsi108_read_reg(TSI108_PCI_OFFSET +
|
||||
TSI108_PCI_IRP_INTAD) & 0xf;
|
||||
mb();
|
||||
for (i = 0; i < 4; i++, mask++) {
|
||||
if (temp & (1 << mask % 4)) {
|
||||
irq = IRQ_PCI_INTA + mask % 4;
|
||||
mask++;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable interrupts from PCI block */
|
||||
temp = tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
|
||||
tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
|
||||
temp & ~TSI108_PCI_IRP_ENABLE_P_INT);
|
||||
mb();
|
||||
(void)tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
|
||||
mb();
|
||||
}
|
||||
#ifdef DEBUG
|
||||
else {
|
||||
printk("TSI108_PIC: error in TSI108_PCI_IRP_STAT\n");
|
||||
pci_irp_stat =
|
||||
tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_STAT);
|
||||
temp =
|
||||
tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_INTAD);
|
||||
mb();
|
||||
printk(">> stat=0x%08x intad=0x%08x ", pci_irp_stat, temp);
|
||||
temp =
|
||||
tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_CFG_CTL);
|
||||
mb();
|
||||
printk("cfg_ctl=0x%08x ", temp);
|
||||
temp =
|
||||
tsi108_read_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE);
|
||||
mb();
|
||||
printk("irp_enable=0x%08x\n", temp);
|
||||
}
|
||||
#endif /* end of DEBUG */
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Linux descriptor level callbacks
|
||||
*/
|
||||
|
||||
static void tsi108_pci_irq_enable(u_int irq)
|
||||
{
|
||||
tsi108_pci_int_unmask(irq);
|
||||
}
|
||||
|
||||
static void tsi108_pci_irq_disable(u_int irq)
|
||||
{
|
||||
tsi108_pci_int_mask(irq);
|
||||
}
|
||||
|
||||
static void tsi108_pci_irq_ack(u_int irq)
|
||||
{
|
||||
tsi108_pci_int_mask(irq);
|
||||
}
|
||||
|
||||
static void tsi108_pci_irq_end(u_int irq)
|
||||
{
|
||||
tsi108_pci_int_unmask(irq);
|
||||
|
||||
/* Enable interrupts from PCI block */
|
||||
tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
|
||||
tsi108_read_reg(TSI108_PCI_OFFSET +
|
||||
TSI108_PCI_IRP_ENABLE) |
|
||||
TSI108_PCI_IRP_ENABLE_P_INT);
|
||||
mb();
|
||||
}
|
||||
|
||||
/*
|
||||
* Interrupt controller descriptor for cascaded PCI interrupt controller.
|
||||
*/
|
||||
|
||||
struct hw_interrupt_type tsi108_pci_irq = {
|
||||
.typename = "tsi108_PCI_int",
|
||||
.enable = tsi108_pci_irq_enable,
|
||||
.disable = tsi108_pci_irq_disable,
|
||||
.ack = tsi108_pci_irq_ack,
|
||||
.end = tsi108_pci_irq_end,
|
||||
};
|
||||
|
||||
/*
|
||||
* Exported functions
|
||||
*/
|
||||
|
||||
/*
|
||||
* The Tsi108 PCI interrupts initialization routine.
|
||||
*
|
||||
* The INTA# - INTD# interrupts on the PCI bus are reported by the PCI block
|
||||
* to the MPIC using single interrupt source (IRQ_TSI108_PCI). Therefore the
|
||||
* PCI block has to be treated as a cascaded interrupt controller connected
|
||||
* to the MPIC.
|
||||
*/
|
||||
|
||||
void __init tsi108_pci_int_init(void)
|
||||
{
|
||||
u_int i;
|
||||
|
||||
DBG("Tsi108_pci_int_init: initializing PCI interrupts\n");
|
||||
|
||||
for (i = 0; i < NUM_PCI_IRQS; i++) {
|
||||
irq_desc[i + IRQ_PCI_INTAD_BASE].handler = &tsi108_pci_irq;
|
||||
irq_desc[i + IRQ_PCI_INTAD_BASE].status |= IRQ_LEVEL;
|
||||
}
|
||||
|
||||
init_pci_source();
|
||||
}
|
||||
|
||||
int tsi108_irq_cascade(struct pt_regs *regs, void *unused)
|
||||
{
|
||||
return get_pci_source();
|
||||
}
|
||||
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