Merge tag 'zxdrm-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into drm-next
ZTE DRM driver updates for 4.11: - Add missing selection of VIDEOMODE_HELPERS in Kconfig, since ZTE DRM driver uses drm_display_mode_to_videomode(). - Enable HDMI audio support through SPDIF interface based on generic hdmi-audio-codec driver. - Enable VOU VL (Video Layer) to support overlay plane with scaling function. - Refine zx_vou driver a bit and then add TV Encoder output device support. [airlied: fixup plane format change] * tag 'zxdrm-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: drm: zte: add tvenc driver support dt: add bindings for ZTE tvenc device drm: zte: add function to configure vou_ctrl dividers drm: zte: move struct vou_inf into zx_vou driver drm: zte: add interlace mode support drm: zte: add overlay plane support drm: zte: add .atomic_disable hook to disable graphic layer drm: zte: make zx_plane accessible from zx_vou driver drm: zte: support hdmi audio through spdif drm: zte: select VIDEOMODE_HELPERS in Kconfig
このコミットが含まれているのは:
Dave Airlie
@@ -21,16 +21,6 @@
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#include "zx_plane_regs.h"
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#include "zx_vou.h"
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struct zx_plane {
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struct drm_plane plane;
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void __iomem *layer;
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void __iomem *csc;
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void __iomem *hbsc;
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void __iomem *rsz;
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};
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#define to_zx_plane(plane) container_of(plane, struct zx_plane, plane)
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static const uint32_t gl_formats[] = {
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_XRGB8888,
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@@ -40,6 +30,261 @@ static const uint32_t gl_formats[] = {
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DRM_FORMAT_ARGB4444,
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};
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static const uint32_t vl_formats[] = {
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DRM_FORMAT_NV12, /* Semi-planar YUV420 */
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DRM_FORMAT_YUV420, /* Planar YUV420 */
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DRM_FORMAT_YUYV, /* Packed YUV422 */
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DRM_FORMAT_YVYU,
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DRM_FORMAT_UYVY,
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DRM_FORMAT_VYUY,
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DRM_FORMAT_YUV444, /* YUV444 8bit */
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/*
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* TODO: add formats below that HW supports:
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* - YUV420 P010
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* - YUV420 Hantro
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* - YUV444 10bit
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*/
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};
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#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
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static int zx_vl_plane_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *plane_state)
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{
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struct drm_framebuffer *fb = plane_state->fb;
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struct drm_crtc *crtc = plane_state->crtc;
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struct drm_crtc_state *crtc_state;
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struct drm_rect clip;
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int min_scale = FRAC_16_16(1, 8);
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int max_scale = FRAC_16_16(8, 1);
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if (!crtc || !fb)
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return 0;
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crtc_state = drm_atomic_get_existing_crtc_state(plane_state->state,
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crtc);
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if (WARN_ON(!crtc_state))
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return -EINVAL;
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/* nothing to check when disabling or disabled */
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if (!crtc_state->enable)
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return 0;
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/* plane must be enabled */
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if (!plane_state->crtc)
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return -EINVAL;
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clip.x1 = 0;
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clip.y1 = 0;
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clip.x2 = crtc_state->adjusted_mode.hdisplay;
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clip.y2 = crtc_state->adjusted_mode.vdisplay;
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return drm_plane_helper_check_state(plane_state, &clip,
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min_scale, max_scale,
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true, true);
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}
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static int zx_vl_get_fmt(uint32_t format)
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{
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switch (format) {
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case DRM_FORMAT_NV12:
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return VL_FMT_YUV420;
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case DRM_FORMAT_YUV420:
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return VL_YUV420_PLANAR | VL_FMT_YUV420;
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case DRM_FORMAT_YUYV:
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return VL_YUV422_YUYV | VL_FMT_YUV422;
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case DRM_FORMAT_YVYU:
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return VL_YUV422_YVYU | VL_FMT_YUV422;
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case DRM_FORMAT_UYVY:
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return VL_YUV422_UYVY | VL_FMT_YUV422;
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case DRM_FORMAT_VYUY:
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return VL_YUV422_VYUY | VL_FMT_YUV422;
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case DRM_FORMAT_YUV444:
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return VL_FMT_YUV444_8BIT;
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default:
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WARN_ONCE(1, "invalid pixel format %d\n", format);
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return -EINVAL;
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}
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}
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static inline void zx_vl_set_update(struct zx_plane *zplane)
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{
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void __iomem *layer = zplane->layer;
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zx_writel_mask(layer + VL_CTRL0, VL_UPDATE, VL_UPDATE);
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}
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static inline void zx_vl_rsz_set_update(struct zx_plane *zplane)
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{
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zx_writel(zplane->rsz + RSZ_VL_ENABLE_CFG, 1);
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}
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static int zx_vl_rsz_get_fmt(uint32_t format)
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{
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switch (format) {
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case DRM_FORMAT_NV12:
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case DRM_FORMAT_YUV420:
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return RSZ_VL_FMT_YCBCR420;
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case DRM_FORMAT_YUYV:
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case DRM_FORMAT_YVYU:
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case DRM_FORMAT_UYVY:
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case DRM_FORMAT_VYUY:
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return RSZ_VL_FMT_YCBCR422;
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case DRM_FORMAT_YUV444:
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return RSZ_VL_FMT_YCBCR444;
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default:
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WARN_ONCE(1, "invalid pixel format %d\n", format);
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return -EINVAL;
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}
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}
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static inline u32 rsz_step_value(u32 src, u32 dst)
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{
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u32 val = 0;
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if (src == dst)
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val = 0;
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else if (src < dst)
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val = RSZ_PARA_STEP((src << 16) / dst);
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else if (src > dst)
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val = RSZ_DATA_STEP(src / dst) |
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RSZ_PARA_STEP(((src << 16) / dst) & 0xffff);
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return val;
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}
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static void zx_vl_rsz_setup(struct zx_plane *zplane, uint32_t format,
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u32 src_w, u32 src_h, u32 dst_w, u32 dst_h)
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{
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void __iomem *rsz = zplane->rsz;
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u32 src_chroma_w = src_w;
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u32 src_chroma_h = src_h;
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u32 fmt;
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/* Set up source and destination resolution */
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zx_writel(rsz + RSZ_SRC_CFG, RSZ_VER(src_h - 1) | RSZ_HOR(src_w - 1));
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zx_writel(rsz + RSZ_DEST_CFG, RSZ_VER(dst_h - 1) | RSZ_HOR(dst_w - 1));
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/* Configure data format for VL RSZ */
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fmt = zx_vl_rsz_get_fmt(format);
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if (fmt >= 0)
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zx_writel_mask(rsz + RSZ_VL_CTRL_CFG, RSZ_VL_FMT_MASK, fmt);
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/* Calculate Chroma height and width */
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if (fmt == RSZ_VL_FMT_YCBCR420) {
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src_chroma_w = src_w >> 1;
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src_chroma_h = src_h >> 1;
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} else if (fmt == RSZ_VL_FMT_YCBCR422) {
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src_chroma_w = src_w >> 1;
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}
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/* Set up Luma and Chroma step registers */
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zx_writel(rsz + RSZ_VL_LUMA_HOR, rsz_step_value(src_w, dst_w));
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zx_writel(rsz + RSZ_VL_LUMA_VER, rsz_step_value(src_h, dst_h));
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zx_writel(rsz + RSZ_VL_CHROMA_HOR, rsz_step_value(src_chroma_w, dst_w));
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zx_writel(rsz + RSZ_VL_CHROMA_VER, rsz_step_value(src_chroma_h, dst_h));
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zx_vl_rsz_set_update(zplane);
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}
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static void zx_vl_plane_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct zx_plane *zplane = to_zx_plane(plane);
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = state->fb;
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struct drm_rect *src = &state->src;
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struct drm_rect *dst = &state->dst;
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struct drm_gem_cma_object *cma_obj;
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void __iomem *layer = zplane->layer;
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void __iomem *hbsc = zplane->hbsc;
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void __iomem *paddr_reg;
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dma_addr_t paddr;
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u32 src_x, src_y, src_w, src_h;
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u32 dst_x, dst_y, dst_w, dst_h;
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uint32_t format;
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u32 fmt;
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int num_planes;
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int i;
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if (!fb)
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return;
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format = fb->format->format;
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src_x = src->x1 >> 16;
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src_y = src->y1 >> 16;
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src_w = drm_rect_width(src) >> 16;
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src_h = drm_rect_height(src) >> 16;
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dst_x = dst->x1;
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dst_y = dst->y1;
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dst_w = drm_rect_width(dst);
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dst_h = drm_rect_height(dst);
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/* Set up data address registers for Y, Cb and Cr planes */
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num_planes = drm_format_num_planes(format);
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paddr_reg = layer + VL_Y;
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for (i = 0; i < num_planes; i++) {
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cma_obj = drm_fb_cma_get_gem_obj(fb, i);
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paddr = cma_obj->paddr + fb->offsets[i];
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paddr += src_y * fb->pitches[i];
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paddr += src_x * drm_format_plane_cpp(format, i);
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zx_writel(paddr_reg, paddr);
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paddr_reg += 4;
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}
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/* Set up source height/width register */
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zx_writel(layer + VL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h));
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/* Set up start position register */
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zx_writel(layer + VL_POS_START, GL_POS_X(dst_x) | GL_POS_Y(dst_y));
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/* Set up end position register */
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zx_writel(layer + VL_POS_END,
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GL_POS_X(dst_x + dst_w) | GL_POS_Y(dst_y + dst_h));
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/* Strides of Cb and Cr planes should be identical */
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zx_writel(layer + VL_STRIDE, LUMA_STRIDE(fb->pitches[0]) |
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CHROMA_STRIDE(fb->pitches[1]));
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/* Set up video layer data format */
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fmt = zx_vl_get_fmt(format);
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if (fmt >= 0)
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zx_writel(layer + VL_CTRL1, fmt);
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/* Always use scaler since it exists (set for not bypass) */
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zx_writel_mask(layer + VL_CTRL2, VL_SCALER_BYPASS_MODE,
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VL_SCALER_BYPASS_MODE);
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zx_vl_rsz_setup(zplane, format, src_w, src_h, dst_w, dst_h);
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/* Enable HBSC block */
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zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, HBSC_CTRL_EN);
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zx_vou_layer_enable(plane);
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zx_vl_set_update(zplane);
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}
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static void zx_plane_atomic_disable(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct zx_plane *zplane = to_zx_plane(plane);
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void __iomem *hbsc = zplane->hbsc;
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zx_vou_layer_disable(plane);
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/* Disable HBSC block */
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zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, 0);
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}
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static const struct drm_plane_helper_funcs zx_vl_plane_helper_funcs = {
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.atomic_check = zx_vl_plane_atomic_check,
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.atomic_update = zx_vl_plane_atomic_update,
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.atomic_disable = zx_plane_atomic_disable,
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};
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static int zx_gl_plane_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *plane_state)
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{
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@@ -107,14 +352,6 @@ static inline void zx_gl_rsz_set_update(struct zx_plane *zplane)
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zx_writel(zplane->rsz + RSZ_ENABLE_CFG, 1);
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}
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void zx_plane_set_update(struct drm_plane *plane)
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{
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struct zx_plane *zplane = to_zx_plane(plane);
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zx_gl_rsz_set_update(zplane);
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zx_gl_set_update(zplane);
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}
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static void zx_gl_rsz_setup(struct zx_plane *zplane, u32 src_w, u32 src_h,
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u32 dst_w, u32 dst_h)
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{
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@@ -207,12 +444,15 @@ static void zx_gl_plane_atomic_update(struct drm_plane *plane,
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/* Enable HBSC block */
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zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, HBSC_CTRL_EN);
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zx_vou_layer_enable(plane);
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zx_gl_set_update(zplane);
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}
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static const struct drm_plane_helper_funcs zx_gl_plane_helper_funcs = {
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.atomic_check = zx_gl_plane_atomic_check,
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.atomic_update = zx_gl_plane_atomic_update,
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.atomic_disable = zx_plane_atomic_disable,
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};
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static void zx_plane_destroy(struct drm_plane *plane)
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@@ -230,6 +470,28 @@ static const struct drm_plane_funcs zx_plane_funcs = {
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.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
|
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};
|
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|
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void zx_plane_set_update(struct drm_plane *plane)
|
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{
|
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struct zx_plane *zplane = to_zx_plane(plane);
|
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/* Do nothing if the plane is not enabled */
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if (!plane->state->crtc)
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return;
|
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|
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switch (plane->type) {
|
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case DRM_PLANE_TYPE_PRIMARY:
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zx_gl_rsz_set_update(zplane);
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zx_gl_set_update(zplane);
|
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break;
|
||||
case DRM_PLANE_TYPE_OVERLAY:
|
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zx_vl_rsz_set_update(zplane);
|
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zx_vl_set_update(zplane);
|
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break;
|
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default:
|
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WARN_ONCE(1, "unsupported plane type %d\n", plane->type);
|
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}
|
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}
|
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|
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static void zx_plane_hbsc_init(struct zx_plane *zplane)
|
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{
|
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void __iomem *hbsc = zplane->hbsc;
|
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@@ -248,28 +510,16 @@ static void zx_plane_hbsc_init(struct zx_plane *zplane)
|
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zx_writel(hbsc + HBSC_THRESHOLD_COL3, (0x3c0 << 16) | 0x40);
|
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}
|
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|
||||
struct drm_plane *zx_plane_init(struct drm_device *drm, struct device *dev,
|
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struct zx_layer_data *data,
|
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enum drm_plane_type type)
|
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int zx_plane_init(struct drm_device *drm, struct zx_plane *zplane,
|
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enum drm_plane_type type)
|
||||
{
|
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const struct drm_plane_helper_funcs *helper;
|
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struct zx_plane *zplane;
|
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struct drm_plane *plane;
|
||||
struct drm_plane *plane = &zplane->plane;
|
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struct device *dev = zplane->dev;
|
||||
const uint32_t *formats;
|
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unsigned int format_count;
|
||||
int ret;
|
||||
|
||||
zplane = devm_kzalloc(dev, sizeof(*zplane), GFP_KERNEL);
|
||||
if (!zplane)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
plane = &zplane->plane;
|
||||
|
||||
zplane->layer = data->layer;
|
||||
zplane->hbsc = data->hbsc;
|
||||
zplane->csc = data->csc;
|
||||
zplane->rsz = data->rsz;
|
||||
|
||||
zx_plane_hbsc_init(zplane);
|
||||
|
||||
switch (type) {
|
||||
@@ -279,10 +529,12 @@ struct drm_plane *zx_plane_init(struct drm_device *drm, struct device *dev,
|
||||
format_count = ARRAY_SIZE(gl_formats);
|
||||
break;
|
||||
case DRM_PLANE_TYPE_OVERLAY:
|
||||
/* TODO: add video layer (vl) support */
|
||||
helper = &zx_vl_plane_helper_funcs;
|
||||
formats = vl_formats;
|
||||
format_count = ARRAY_SIZE(vl_formats);
|
||||
break;
|
||||
default:
|
||||
return ERR_PTR(-ENODEV);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = drm_universal_plane_init(drm, plane, VOU_CRTC_MASK,
|
||||
@@ -290,10 +542,10 @@ struct drm_plane *zx_plane_init(struct drm_device *drm, struct device *dev,
|
||||
type, NULL);
|
||||
if (ret) {
|
||||
DRM_DEV_ERROR(dev, "failed to init universal plane: %d\n", ret);
|
||||
return ERR_PTR(ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
drm_plane_helper_add(plane, helper);
|
||||
|
||||
return plane;
|
||||
return 0;
|
||||
}
|
||||
|
||||
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