Merge tag 'davinci-for-v3.16/edma' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers
Merge "DaVinci EDMA clean-up for v3.16" from Sekhar Nori: This series makes edma use configuration information available within the IP instead of reading it from platform data or DT. Some other useful clean-ups are included too. * tag 'davinci-for-v3.16/edma' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: (34 commits) ARM: edma: Remove redundant/unused parameters from edma_soc_info ARM: davinci: Remove redundant/unused parameters for edma ARM: dts: am4372: Remove obsolete properties from edma node ARM: dts: am33xx: Remove obsolete properties from edma node dt/bindings: ti,edma: Remove redundant properties from documentation ARM: edma: Get IP configuration from HW (number of channels, tc, etc) ARM: edma: Save number of regions from pdata to struct edma ARM: edma: Remove num_cc member from struct edma ARM: edma: Remove queue_tc_mapping data from edma_soc_info ARM: davinci: Remove eDMA3 queue_tc_mapping data from edma_soc_info ARM: edma: Do not change TC -> Queue mapping, leave it to default. ARM: edma: Take the number of tc from edma_soc_info (pdata) ARM: edma: No need to clean the pdata in edma_of_parse_dt() ARM: edma: Clean up and simplify the code around irq request dmaengine: edma: update DMA memcpy to use new param element dmaengine: edma: Document variables used for residue accounting dmaengine: edma: Provide granular accounting dmaengine: edma: Make reading the position of active channels work dmaengine: edma: Store transfer data in edma_desc and edma_pset dmaengine: edma: Create private pset struct ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
@@ -102,7 +102,13 @@
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#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
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#define EDMA_DCHMAP 0x0100 /* 64 registers */
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#define CHMAP_EXIST BIT(24)
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/* CCCFG register */
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#define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
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#define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
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#define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
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#define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
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#define CHMAP_EXIST BIT(24)
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#define EDMA_MAX_DMACH 64
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#define EDMA_MAX_PARAMENTRY 512
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@@ -233,7 +239,6 @@ struct edma {
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unsigned num_region;
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unsigned num_slots;
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unsigned num_tc;
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unsigned num_cc;
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enum dma_event_q default_queue;
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/* list of channels with no even trigger; terminated by "-1" */
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@@ -290,12 +295,6 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
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~(0x7 << bit), queue_no << bit);
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}
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static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
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{
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int bit = queue_no * 4;
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edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
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}
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static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
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int priority)
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{
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@@ -994,29 +993,23 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port,
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EXPORT_SYMBOL(edma_set_dest);
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/**
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* edma_get_position - returns the current transfer points
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* edma_get_position - returns the current transfer point
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* @slot: parameter RAM slot being examined
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* @src: pointer to source port position
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* @dst: pointer to destination port position
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* @dst: true selects the dest position, false the source
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*
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* Returns current source and destination addresses for a particular
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* parameter RAM slot. Its channel should not be active when this is called.
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* Returns the position of the current active slot
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*/
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void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
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dma_addr_t edma_get_position(unsigned slot, bool dst)
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{
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struct edmacc_param temp;
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unsigned ctlr;
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u32 offs, ctlr = EDMA_CTLR(slot);
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ctlr = EDMA_CTLR(slot);
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slot = EDMA_CHAN_SLOT(slot);
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edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
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if (src != NULL)
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*src = temp.src;
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if (dst != NULL)
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*dst = temp.dst;
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offs = PARM_OFFSET(slot);
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offs += dst ? PARM_DST : PARM_SRC;
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return edma_read(ctlr, offs);
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}
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EXPORT_SYMBOL(edma_get_position);
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/**
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* edma_set_src_index - configure DMA source address indexing
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@@ -1421,6 +1414,67 @@ void edma_clear_event(unsigned channel)
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}
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EXPORT_SYMBOL(edma_clear_event);
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static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
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struct edma *edma_cc)
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{
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int i;
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u32 value, cccfg;
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s8 (*queue_priority_map)[2];
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/* Decode the eDMA3 configuration from CCCFG register */
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cccfg = edma_read(0, EDMA_CCCFG);
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value = GET_NUM_REGN(cccfg);
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edma_cc->num_region = BIT(value);
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value = GET_NUM_DMACH(cccfg);
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edma_cc->num_channels = BIT(value + 1);
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value = GET_NUM_PAENTRY(cccfg);
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edma_cc->num_slots = BIT(value + 4);
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value = GET_NUM_EVQUE(cccfg);
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edma_cc->num_tc = value + 1;
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dev_dbg(dev, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg);
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dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
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dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
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dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
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dev_dbg(dev, "num_tc: %u\n", edma_cc->num_tc);
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/* Nothing need to be done if queue priority is provided */
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if (pdata->queue_priority_mapping)
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return 0;
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/*
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* Configure TC/queue priority as follows:
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* Q0 - priority 0
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* Q1 - priority 1
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* Q2 - priority 2
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* ...
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* The meaning of priority numbers: 0 highest priority, 7 lowest
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* priority. So Q0 is the highest priority queue and the last queue has
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* the lowest priority.
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*/
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queue_priority_map = devm_kzalloc(dev,
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(edma_cc->num_tc + 1) * sizeof(s8),
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GFP_KERNEL);
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if (!queue_priority_map)
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return -ENOMEM;
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for (i = 0; i < edma_cc->num_tc; i++) {
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queue_priority_map[i][0] = i;
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queue_priority_map[i][1] = i;
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}
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queue_priority_map[i][0] = -1;
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queue_priority_map[i][1] = -1;
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pdata->queue_priority_mapping = queue_priority_map;
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pdata->default_queue = 0;
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return 0;
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}
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#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
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static int edma_xbar_event_map(struct device *dev, struct device_node *node,
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@@ -1471,65 +1525,16 @@ static int edma_of_parse_dt(struct device *dev,
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struct device_node *node,
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struct edma_soc_info *pdata)
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{
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int ret = 0, i;
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u32 value;
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int ret = 0;
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struct property *prop;
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size_t sz;
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struct edma_rsv_info *rsv_info;
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s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
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memset(pdata, 0, sizeof(struct edma_soc_info));
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ret = of_property_read_u32(node, "dma-channels", &value);
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if (ret < 0)
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return ret;
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pdata->n_channel = value;
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ret = of_property_read_u32(node, "ti,edma-regions", &value);
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if (ret < 0)
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return ret;
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pdata->n_region = value;
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ret = of_property_read_u32(node, "ti,edma-slots", &value);
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if (ret < 0)
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return ret;
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pdata->n_slot = value;
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pdata->n_cc = 1;
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rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
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if (!rsv_info)
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return -ENOMEM;
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pdata->rsv = rsv_info;
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queue_tc_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
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if (!queue_tc_map)
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return -ENOMEM;
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for (i = 0; i < 3; i++) {
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queue_tc_map[i][0] = i;
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queue_tc_map[i][1] = i;
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}
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queue_tc_map[i][0] = -1;
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queue_tc_map[i][1] = -1;
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pdata->queue_tc_mapping = queue_tc_map;
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queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
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if (!queue_priority_map)
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return -ENOMEM;
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for (i = 0; i < 3; i++) {
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queue_priority_map[i][0] = i;
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queue_priority_map[i][1] = i;
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}
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queue_priority_map[i][0] = -1;
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queue_priority_map[i][1] = -1;
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pdata->queue_priority_mapping = queue_priority_map;
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pdata->default_queue = 0;
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prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
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if (prop)
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ret = edma_xbar_event_map(dev, node, pdata, sz);
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@@ -1556,6 +1561,7 @@ static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
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return ERR_PTR(ret);
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dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
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dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
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of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
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&edma_filter_info);
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@@ -1574,7 +1580,6 @@ static int edma_probe(struct platform_device *pdev)
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struct edma_soc_info **info = pdev->dev.platform_data;
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struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL};
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s8 (*queue_priority_mapping)[2];
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s8 (*queue_tc_mapping)[2];
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int i, j, off, ln, found = 0;
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int status = -1;
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const s16 (*rsv_chans)[2];
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@@ -1585,7 +1590,6 @@ static int edma_probe(struct platform_device *pdev)
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struct resource *r[EDMA_MAX_CC] = {NULL};
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struct resource res[EDMA_MAX_CC];
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char res_name[10];
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char irq_name[10];
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struct device_node *node = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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int ret;
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@@ -1650,12 +1654,10 @@ static int edma_probe(struct platform_device *pdev)
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if (!edma_cc[j])
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return -ENOMEM;
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edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
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EDMA_MAX_DMACH);
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edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
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EDMA_MAX_PARAMENTRY);
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edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
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EDMA_MAX_CC);
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/* Get eDMA3 configuration from IP */
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ret = edma_setup_from_hw(dev, info[j], edma_cc[j]);
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if (ret)
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return ret;
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edma_cc[j]->default_queue = info[j]->default_queue;
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@@ -1707,14 +1709,21 @@ static int edma_probe(struct platform_device *pdev)
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if (node) {
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irq[j] = irq_of_parse_and_map(node, 0);
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err_irq[j] = irq_of_parse_and_map(node, 2);
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} else {
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char irq_name[10];
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sprintf(irq_name, "edma%d", j);
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irq[j] = platform_get_irq_byname(pdev, irq_name);
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sprintf(irq_name, "edma%d_err", j);
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err_irq[j] = platform_get_irq_byname(pdev, irq_name);
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}
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edma_cc[j]->irq_res_start = irq[j];
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status = devm_request_irq(&pdev->dev, irq[j],
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dma_irq_handler, 0, "edma",
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&pdev->dev);
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edma_cc[j]->irq_res_end = err_irq[j];
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status = devm_request_irq(dev, irq[j], dma_irq_handler, 0,
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"edma", dev);
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if (status < 0) {
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dev_dbg(&pdev->dev,
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"devm_request_irq %d failed --> %d\n",
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@@ -1722,16 +1731,8 @@ static int edma_probe(struct platform_device *pdev)
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return status;
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}
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if (node) {
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err_irq[j] = irq_of_parse_and_map(node, 2);
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} else {
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sprintf(irq_name, "edma%d_err", j);
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err_irq[j] = platform_get_irq_byname(pdev, irq_name);
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}
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edma_cc[j]->irq_res_end = err_irq[j];
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status = devm_request_irq(&pdev->dev, err_irq[j],
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dma_ccerr_handler, 0,
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"edma_error", &pdev->dev);
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status = devm_request_irq(dev, err_irq[j], dma_ccerr_handler, 0,
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"edma_error", dev);
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if (status < 0) {
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dev_dbg(&pdev->dev,
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"devm_request_irq %d failed --> %d\n",
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@@ -1742,14 +1743,8 @@ static int edma_probe(struct platform_device *pdev)
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for (i = 0; i < edma_cc[j]->num_channels; i++)
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map_dmach_queue(j, i, info[j]->default_queue);
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queue_tc_mapping = info[j]->queue_tc_mapping;
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queue_priority_mapping = info[j]->queue_priority_mapping;
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/* Event queue to TC mapping */
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for (i = 0; queue_tc_mapping[i][0] != -1; i++)
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map_queue_tc(j, queue_tc_mapping[i][0],
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queue_tc_mapping[i][1]);
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/* Event queue priority mapping */
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for (i = 0; queue_priority_mapping[i][0] != -1; i++)
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assign_priority_to_queue(j,
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@@ -1762,7 +1757,7 @@ static int edma_probe(struct platform_device *pdev)
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if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
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map_dmach_param(j);
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for (i = 0; i < info[j]->n_region; i++) {
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for (i = 0; i < edma_cc[j]->num_region; i++) {
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edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
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edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
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edma_write_array(j, EDMA_QRAE, i, 0x0);
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