[PATCH] i386/x86-64: Generalize X86_FEATURE_CONSTANT_TSC flag
Define it for i386 too. This is a synthetic flag that signifies that the CPU's TSC runs at a constant P state invariant frequency. Fix up the logic on x86-64/i386 to set it on all known CPUs. Use the AMD defined bit to set it on future AMD CPUs. Cc: venkatesh.pallipadi@intel.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:

committed by
Linus Torvalds

parent
2d52ede987
commit
39b3a79105
@@ -216,6 +216,11 @@ static void __init init_amd(struct cpuinfo_x86 *c)
|
||||
c->x86_max_cores = 1;
|
||||
}
|
||||
|
||||
if (cpuid_eax(0x80000000) >= 0x80000007) {
|
||||
if (cpuid_edx(0x80000007) & (1<<8))
|
||||
set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_HT
|
||||
/*
|
||||
* On a AMD dual core setup the lower bits of the APIC id
|
||||
@@ -233,6 +238,7 @@ static void __init init_amd(struct cpuinfo_x86 *c)
|
||||
cpu, c->x86_max_cores, cpu_core_id[cpu]);
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
|
||||
|
Reference in New Issue
Block a user