Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "This contains driver changes that are tightly connected to SoC
  specific code. Aside from smaller cleanups and bug fixes, here is a
  list of the notable changes.

  New device drivers:

   - The Turris Mox router has a new "moxtet" bus driver for its
     on-board pluggable extension bus. The same platform also gains a
     firmware driver.

   - The Samsung Exynos family gains a new Chipid driver exporting using
     the soc device sysfs interface

   - A similar socinfo driver for Qualcomm Snapdragon chips.

   - A firmware driver for the NXP i.MX DSP IPC protocol using shared
     memory and a mailbox

  Other changes:

   - The i.MX reset controller driver now supports the NXP i.MX8MM chip

   - Amlogic SoC specific drivers gain support for the S905X3 and A311D
     chips

   - A rework of the TI Davinci framebuffer driver to allow important
     cleanups in the platform code

   - A couple of device drivers for removed ARM SoC platforms are
     removed. Most of the removals were picked up by other maintainers,
     this contains whatever was left"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (123 commits)
  bus: uniphier-system-bus: use devm_platform_ioremap_resource()
  soc: ti: ti_sci_pm_domains: Add support for exclusive and shared access
  dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared access
  firmware: ti_sci: Allow for device shared and exclusive requests
  bus: imx-weim: remove incorrect __init annotations
  fbdev: remove w90x900/nuc900 platform drivers
  spi: remove w90x900 driver
  net: remove w90p910-ether driver
  net: remove ks8695 driver
  firmware: turris-mox-rwtm: Add sysfs documentation
  firmware: Add Turris Mox rWTM firmware driver
  dt-bindings: firmware: Document cznic,turris-mox-rwtm binding
  bus: moxtet: fix unsigned comparison to less than zero
  bus: moxtet: remove set but not used variable 'dummy'
  ARM: scoop: Use the right include
  dt-bindings: power: add Amlogic Everything-Else power domains bindings
  soc: amlogic: Add support for Everything-Else power domains controller
  fbdev: da8xx: use resource management for dma
  fbdev: da8xx-fb: drop a redundant if
  fbdev: da8xx-fb: use devm_platform_ioremap_resource()
  ...
This commit is contained in:
Linus Torvalds
2019-09-16 15:52:38 -07:00
128 changed files with 5518 additions and 5063 deletions

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@@ -0,0 +1,67 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
*
* Header file for the DSP IPC implementation
*/
#ifndef _IMX_DSP_IPC_H
#define _IMX_DSP_IPC_H
#include <linux/device.h>
#include <linux/types.h>
#include <linux/mailbox_client.h>
#define DSP_MU_CHAN_NUM 4
struct imx_dsp_chan {
struct imx_dsp_ipc *ipc;
struct mbox_client cl;
struct mbox_chan *ch;
char *name;
int idx;
};
struct imx_dsp_ops {
void (*handle_reply)(struct imx_dsp_ipc *ipc);
void (*handle_request)(struct imx_dsp_ipc *ipc);
};
struct imx_dsp_ipc {
/* Host <-> DSP communication uses 2 txdb and 2 rxdb channels */
struct imx_dsp_chan chans[DSP_MU_CHAN_NUM];
struct device *dev;
struct imx_dsp_ops *ops;
void *private_data;
};
static inline void imx_dsp_set_data(struct imx_dsp_ipc *ipc, void *data)
{
if (!ipc)
return;
ipc->private_data = data;
}
static inline void *imx_dsp_get_data(struct imx_dsp_ipc *ipc)
{
if (!ipc)
return NULL;
return ipc->private_data;
}
#if IS_ENABLED(CONFIG_IMX_DSP)
int imx_dsp_ring_doorbell(struct imx_dsp_ipc *dsp, unsigned int chan_idx);
#else
static inline int imx_dsp_ring_doorbell(struct imx_dsp_ipc *ipc,
unsigned int chan_idx)
{
return -ENOTSUPP;
}
#endif
#endif /* _IMX_DSP_IPC_H */

109
include/linux/moxtet.h Normal file
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@@ -0,0 +1,109 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Turris Mox module configuration bus driver
*
* Copyright (C) 2019 Marek Behun <marek.behun@nic.cz>
*/
#ifndef __LINUX_MOXTET_H
#define __LINUX_MOXTET_H
#include <linux/device.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/mutex.h>
#define TURRIS_MOX_MAX_MODULES 10
enum turris_mox_cpu_module_id {
TURRIS_MOX_CPU_ID_EMMC = 0x00,
TURRIS_MOX_CPU_ID_SD = 0x10,
};
enum turris_mox_module_id {
TURRIS_MOX_MODULE_FIRST = 0x01,
TURRIS_MOX_MODULE_SFP = 0x01,
TURRIS_MOX_MODULE_PCI = 0x02,
TURRIS_MOX_MODULE_TOPAZ = 0x03,
TURRIS_MOX_MODULE_PERIDOT = 0x04,
TURRIS_MOX_MODULE_USB3 = 0x05,
TURRIS_MOX_MODULE_PCI_BRIDGE = 0x06,
TURRIS_MOX_MODULE_LAST = 0x06,
};
#define MOXTET_NIRQS 16
extern struct bus_type moxtet_type;
struct moxtet {
struct device *dev;
struct mutex lock;
u8 modules[TURRIS_MOX_MAX_MODULES];
int count;
u8 tx[TURRIS_MOX_MAX_MODULES];
int dev_irq;
struct {
struct irq_domain *domain;
struct irq_chip chip;
unsigned long masked, exists;
struct moxtet_irqpos {
u8 idx;
u8 bit;
} position[MOXTET_NIRQS];
} irq;
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_root;
#endif
};
struct moxtet_driver {
const enum turris_mox_module_id *id_table;
struct device_driver driver;
};
static inline struct moxtet_driver *
to_moxtet_driver(struct device_driver *drv)
{
if (!drv)
return NULL;
return container_of(drv, struct moxtet_driver, driver);
}
extern int __moxtet_register_driver(struct module *owner,
struct moxtet_driver *mdrv);
static inline void moxtet_unregister_driver(struct moxtet_driver *mdrv)
{
if (mdrv)
driver_unregister(&mdrv->driver);
}
#define moxtet_register_driver(driver) \
__moxtet_register_driver(THIS_MODULE, driver)
#define module_moxtet_driver(__moxtet_driver) \
module_driver(__moxtet_driver, moxtet_register_driver, \
moxtet_unregister_driver)
struct moxtet_device {
struct device dev;
struct moxtet *moxtet;
enum turris_mox_module_id id;
unsigned int idx;
};
extern int moxtet_device_read(struct device *dev);
extern int moxtet_device_write(struct device *dev, u8 val);
extern int moxtet_device_written(struct device *dev);
static inline struct moxtet_device *
to_moxtet_device(struct device *dev)
{
if (!dev)
return NULL;
return container_of(dev, struct moxtet_device, dev);
}
#endif /* __LINUX_MOXTET_H */

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@@ -1,29 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2009 Nuvoton technology corporation.
*
* Wan ZongShun <mcuos.com@gmail.com>
*/
#ifndef __SPI_NUC900_H
#define __SPI_NUC900_H
extern void mfp_set_groupg(struct device *dev, const char *subname);
struct nuc900_spi_info {
unsigned int num_cs;
unsigned int lsb;
unsigned int txneg;
unsigned int rxneg;
unsigned int divider;
unsigned int sleep;
unsigned int txnum;
unsigned int txbitlen;
int bus_num;
};
struct nuc900_spi_chip {
unsigned char bits_per_word;
};
#endif /* __SPI_NUC900_H */

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@@ -1,79 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* linux/include/asm/arch-nuc900/fb.h
*
* Copyright (c) 2008 Nuvoton technology corporation
* All rights reserved.
*
* Changelog:
*
* 2008/08/26 vincen.zswan modify this file for LCD.
*/
#ifndef __ASM_ARM_FB_H
#define __ASM_ARM_FB_H
/* LCD Controller Hardware Desc */
struct nuc900fb_hw {
unsigned int lcd_dccs;
unsigned int lcd_device_ctrl;
unsigned int lcd_mpulcd_cmd;
unsigned int lcd_int_cs;
unsigned int lcd_crtc_size;
unsigned int lcd_crtc_dend;
unsigned int lcd_crtc_hr;
unsigned int lcd_crtc_hsync;
unsigned int lcd_crtc_vr;
unsigned int lcd_va_baddr0;
unsigned int lcd_va_baddr1;
unsigned int lcd_va_fbctrl;
unsigned int lcd_va_scale;
unsigned int lcd_va_test;
unsigned int lcd_va_win;
unsigned int lcd_va_stuff;
};
/* LCD Display Description */
struct nuc900fb_display {
/* LCD Image type */
unsigned type;
/* LCD Screen Size */
unsigned short width;
unsigned short height;
/* LCD Screen Info */
unsigned short xres;
unsigned short yres;
unsigned short bpp;
unsigned long pixclock;
unsigned short left_margin;
unsigned short right_margin;
unsigned short hsync_len;
unsigned short upper_margin;
unsigned short lower_margin;
unsigned short vsync_len;
/* hardware special register value */
unsigned int dccs;
unsigned int devctl;
unsigned int fbctrl;
unsigned int scale;
};
struct nuc900fb_mach_info {
struct nuc900fb_display *displays;
unsigned num_displays;
unsigned default_display;
/* GPIO Setting Info */
unsigned gpio_dir;
unsigned gpio_dir_mask;
unsigned gpio_data;
unsigned gpio_data_mask;
};
extern void __init nuc900_fb_set_platdata(struct nuc900fb_mach_info *);
#endif /* __ASM_ARM_FB_H */

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@@ -49,8 +49,9 @@ extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
extern int qcom_scm_pas_shutdown(u32 peripheral);
extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
unsigned int *src, struct qcom_scm_vmperm *newvm,
int dest_cnt);
unsigned int *src,
const struct qcom_scm_vmperm *newvm,
unsigned int dest_cnt);
extern void qcom_scm_cpu_power_down(u32 flags);
extern u32 qcom_scm_get_version(void);
extern int qcom_scm_set_remote_state(u32 state, u32 id);
@@ -87,8 +88,8 @@ qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
static inline int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
unsigned int *src,
struct qcom_scm_vmperm *newvm,
int dest_cnt) { return -ENODEV; }
const struct qcom_scm_vmperm *newvm,
unsigned int dest_cnt) { return -ENODEV; }
static inline void qcom_scm_cpu_power_down(u32 flags) {}
static inline u32 qcom_scm_get_version(void) { return 0; }
static inline u32

View File

@@ -1,4 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* SCMI Message Protocol driver header
*
@@ -71,7 +71,7 @@ struct scmi_clk_ops {
int (*rate_get)(const struct scmi_handle *handle, u32 clk_id,
u64 *rate);
int (*rate_set)(const struct scmi_handle *handle, u32 clk_id,
u32 config, u64 rate);
u64 rate);
int (*enable)(const struct scmi_handle *handle, u32 clk_id);
int (*disable)(const struct scmi_handle *handle, u32 clk_id);
};
@@ -145,6 +145,8 @@ struct scmi_sensor_info {
u32 id;
u8 type;
s8 scale;
u8 num_trip_points;
bool async;
char name[SCMI_MAX_STR_SIZE];
};
@@ -167,9 +169,9 @@ enum scmi_sensor_class {
*
* @count_get: get the count of sensors provided by SCMI
* @info_get: get the information of the specified sensor
* @configuration_set: control notifications on cross-over events for
* @trip_point_notify: control notifications on cross-over events for
* the trip-points
* @trip_point_set: selects and configures a trip-point of interest
* @trip_point_config: selects and configures a trip-point of interest
* @reading_get: gets the current value of the sensor
*/
struct scmi_sensor_ops {
@@ -177,12 +179,32 @@ struct scmi_sensor_ops {
const struct scmi_sensor_info *(*info_get)
(const struct scmi_handle *handle, u32 sensor_id);
int (*configuration_set)(const struct scmi_handle *handle,
u32 sensor_id);
int (*trip_point_set)(const struct scmi_handle *handle, u32 sensor_id,
u8 trip_id, u64 trip_value);
int (*trip_point_notify)(const struct scmi_handle *handle,
u32 sensor_id, bool enable);
int (*trip_point_config)(const struct scmi_handle *handle,
u32 sensor_id, u8 trip_id, u64 trip_value);
int (*reading_get)(const struct scmi_handle *handle, u32 sensor_id,
bool async, u64 *value);
u64 *value);
};
/**
* struct scmi_reset_ops - represents the various operations provided
* by SCMI Reset Protocol
*
* @num_domains_get: get the count of reset domains provided by SCMI
* @name_get: gets the name of a reset domain
* @latency_get: gets the reset latency for the specified reset domain
* @reset: resets the specified reset domain
* @assert: explicitly assert reset signal of the specified reset domain
* @deassert: explicitly deassert reset signal of the specified reset domain
*/
struct scmi_reset_ops {
int (*num_domains_get)(const struct scmi_handle *handle);
char *(*name_get)(const struct scmi_handle *handle, u32 domain);
int (*latency_get)(const struct scmi_handle *handle, u32 domain);
int (*reset)(const struct scmi_handle *handle, u32 domain);
int (*assert)(const struct scmi_handle *handle, u32 domain);
int (*deassert)(const struct scmi_handle *handle, u32 domain);
};
/**
@@ -194,6 +216,7 @@ struct scmi_sensor_ops {
* @perf_ops: pointer to set of performance protocol operations
* @clk_ops: pointer to set of clock protocol operations
* @sensor_ops: pointer to set of sensor protocol operations
* @reset_ops: pointer to set of reset protocol operations
* @perf_priv: pointer to private data structure specific to performance
* protocol(for internal use only)
* @clk_priv: pointer to private data structure specific to clock
@@ -202,6 +225,8 @@ struct scmi_sensor_ops {
* protocol(for internal use only)
* @sensor_priv: pointer to private data structure specific to sensors
* protocol(for internal use only)
* @reset_priv: pointer to private data structure specific to reset
* protocol(for internal use only)
*/
struct scmi_handle {
struct device *dev;
@@ -210,11 +235,13 @@ struct scmi_handle {
struct scmi_clk_ops *clk_ops;
struct scmi_power_ops *power_ops;
struct scmi_sensor_ops *sensor_ops;
struct scmi_reset_ops *reset_ops;
/* for protocol internal use */
void *perf_priv;
void *clk_priv;
void *power_priv;
void *sensor_priv;
void *reset_priv;
};
enum scmi_std_protocol {
@@ -224,6 +251,7 @@ enum scmi_std_protocol {
SCMI_PROTOCOL_PERF = 0x13,
SCMI_PROTOCOL_CLOCK = 0x14,
SCMI_PROTOCOL_SENSOR = 0x15,
SCMI_PROTOCOL_RESET = 0x16,
};
struct scmi_device {

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@@ -63,26 +63,26 @@ void cmdq_pkt_destroy(struct cmdq_pkt *pkt);
/**
* cmdq_pkt_write() - append write command to the CMDQ packet
* @pkt: the CMDQ packet
* @value: the specified target register value
* @subsys: the CMDQ sub system code
* @offset: register offset from CMDQ sub system
* @value: the specified target register value
*
* Return: 0 for success; else the error code is returned
*/
int cmdq_pkt_write(struct cmdq_pkt *pkt, u32 value, u32 subsys, u32 offset);
int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
/**
* cmdq_pkt_write_mask() - append write command with mask to the CMDQ packet
* @pkt: the CMDQ packet
* @value: the specified target register value
* @subsys: the CMDQ sub system code
* @offset: register offset from CMDQ sub system
* @value: the specified target register value
* @mask: the specified target register mask
*
* Return: 0 for success; else the error code is returned
*/
int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
u32 subsys, u32 offset, u32 mask);
int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
u16 offset, u32 value, u32 mask);
/**
* cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
@@ -91,7 +91,7 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u32 value,
*
* Return: 0 for success; else the error code is returned
*/
int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event);
int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
/**
* cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
@@ -100,7 +100,7 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u32 event);
*
* Return: 0 for success; else the error code is returned
*/
int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u32 event);
int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
/**
* cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ

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@@ -0,0 +1,52 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2018 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Exynos - CHIPID support
*/
#ifndef __LINUX_SOC_EXYNOS_CHIPID_H
#define __LINUX_SOC_EXYNOS_CHIPID_H
#define EXYNOS_CHIPID_REG_PRO_ID 0x00
#define EXYNOS_SUBREV_MASK (0xf << 4)
#define EXYNOS_MAINREV_MASK (0xf << 0)
#define EXYNOS_REV_MASK (EXYNOS_SUBREV_MASK | \
EXYNOS_MAINREV_MASK)
#define EXYNOS_MASK 0xfffff000
#define EXYNOS_CHIPID_REG_PKG_ID 0x04
/* Bit field definitions for EXYNOS_CHIPID_REG_PKG_ID register */
#define EXYNOS5422_IDS_OFFSET 24
#define EXYNOS5422_IDS_MASK 0xff
#define EXYNOS5422_USESG_OFFSET 3
#define EXYNOS5422_USESG_MASK 0x01
#define EXYNOS5422_SG_OFFSET 0
#define EXYNOS5422_SG_MASK 0x07
#define EXYNOS5422_TABLE_OFFSET 8
#define EXYNOS5422_TABLE_MASK 0x03
#define EXYNOS5422_SG_A_OFFSET 17
#define EXYNOS5422_SG_A_MASK 0x0f
#define EXYNOS5422_SG_B_OFFSET 21
#define EXYNOS5422_SG_B_MASK 0x03
#define EXYNOS5422_SG_BSIGN_OFFSET 23
#define EXYNOS5422_SG_BSIGN_MASK 0x01
#define EXYNOS5422_BIN2_OFFSET 12
#define EXYNOS5422_BIN2_MASK 0x01
#define EXYNOS_CHIPID_REG_LOT_ID 0x14
#define EXYNOS_CHIPID_REG_AUX_INFO 0x1c
/* Bit field definitions for EXYNOS_CHIPID_REG_AUX_INFO register */
#define EXYNOS5422_TMCB_OFFSET 0
#define EXYNOS5422_TMCB_MASK 0x7f
#define EXYNOS5422_ARM_UP_OFFSET 8
#define EXYNOS5422_ARM_UP_MASK 0x03
#define EXYNOS5422_ARM_DN_OFFSET 10
#define EXYNOS5422_ARM_DN_MASK 0x03
#define EXYNOS5422_KFC_UP_OFFSET 12
#define EXYNOS5422_KFC_UP_MASK 0x03
#define EXYNOS5422_KFC_DN_OFFSET 14
#define EXYNOS5422_KFC_DN_MASK 0x03
#endif /*__LINUX_SOC_EXYNOS_CHIPID_H */

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@@ -97,7 +97,10 @@ struct ti_sci_core_ops {
*/
struct ti_sci_dev_ops {
int (*get_device)(const struct ti_sci_handle *handle, u32 id);
int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
u32 id);
int (*put_device)(const struct ti_sci_handle *handle, u32 id);
int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
int (*get_context_loss_count)(const struct ti_sci_handle *handle,

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@@ -12,6 +12,7 @@ struct soc_device_attribute {
const char *machine;
const char *family;
const char *revision;
const char *serial_number;
const char *soc_id;
const void *data;
};