Merge branch 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull RAS updates from Ingo Molnar: "MCE handling updates, but also some generic drivers/edac/ changes to better organize the Kconfig space" * 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/ras: Move AMD MCE injector to arch/x86/ras/ x86/mce: Add a wrapper around mce_log() for injection x86/mce: Rename rcu_dereference_check_mce() to mce_log_get_idx_check() RAS: Add a menuconfig option with descriptive text x86/mce: Reenable CMCI banks when swiching back to interrupt mode x86/mce: Clear Local MCE opt-in before kexec x86/mce: Remove unused function declarations x86/mce: Kill drain_mcelog_buffer() x86/mce: Avoid potential deadlock due to printk() in MCE context x86/mce: Remove the MCE ring for Action Optional errors x86/mce: Don't use percpu workqueues x86/mce: Provide a lockless memory pool to save error records x86/mce: Reuse one of the u16 padding fields in 'struct mce'
This commit is contained in:
Linus Torvalds
@@ -61,16 +61,6 @@ config EDAC_DECODE_MCE
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which occur really early upon boot, before the module infrastructure
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has been initialized.
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config EDAC_MCE_INJ
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tristate "Simple MCE injection interface"
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depends on EDAC_DECODE_MCE && DEBUG_FS
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default n
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help
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This is a simple debugfs interface to inject MCEs and test different
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aspects of the MCE handling code.
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WARNING: Do not even assume this interface is staying stable!
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config EDAC_MM_EDAC
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tristate "Main Memory EDAC (Error Detection And Correction) reporting"
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select RAS
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@@ -17,7 +17,6 @@ edac_core-y += edac_pci.o edac_pci_sysfs.o
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endif
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obj-$(CONFIG_EDAC_GHES) += ghes_edac.o
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obj-$(CONFIG_EDAC_MCE_INJ) += mce_amd_inj.o
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edac_mce_amd-y := mce_amd.o
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obj-$(CONFIG_EDAC_DECODE_MCE) += edac_mce_amd.o
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@@ -1,375 +0,0 @@
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/*
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* A simple MCE injection facility for testing different aspects of the RAS
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* code. This driver should be built as module so that it can be loaded
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* on production kernels for testing purposes.
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*
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* This file may be distributed under the terms of the GNU General Public
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* License version 2.
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*
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* Copyright (c) 2010-14: Borislav Petkov <bp@alien8.de>
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* Advanced Micro Devices Inc.
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*/
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#include <linux/kobject.h>
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#include <linux/debugfs.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/cpu.h>
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#include <linux/string.h>
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#include <linux/uaccess.h>
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#include <asm/mce.h>
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#include "mce_amd.h"
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/*
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* Collect all the MCi_XXX settings
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*/
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static struct mce i_mce;
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static struct dentry *dfs_inj;
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static u8 n_banks;
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#define MAX_FLAG_OPT_SIZE 3
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enum injection_type {
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SW_INJ = 0, /* SW injection, simply decode the error */
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HW_INJ, /* Trigger a #MC */
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N_INJ_TYPES,
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};
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static const char * const flags_options[] = {
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[SW_INJ] = "sw",
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[HW_INJ] = "hw",
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NULL
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};
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/* Set default injection to SW_INJ */
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static enum injection_type inj_type = SW_INJ;
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#define MCE_INJECT_SET(reg) \
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static int inj_##reg##_set(void *data, u64 val) \
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{ \
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struct mce *m = (struct mce *)data; \
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\
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m->reg = val; \
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return 0; \
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}
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MCE_INJECT_SET(status);
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MCE_INJECT_SET(misc);
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MCE_INJECT_SET(addr);
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#define MCE_INJECT_GET(reg) \
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static int inj_##reg##_get(void *data, u64 *val) \
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{ \
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struct mce *m = (struct mce *)data; \
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\
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*val = m->reg; \
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return 0; \
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}
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MCE_INJECT_GET(status);
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MCE_INJECT_GET(misc);
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MCE_INJECT_GET(addr);
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DEFINE_SIMPLE_ATTRIBUTE(status_fops, inj_status_get, inj_status_set, "%llx\n");
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DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, inj_misc_set, "%llx\n");
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DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n");
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/*
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* Caller needs to be make sure this cpu doesn't disappear
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* from under us, i.e.: get_cpu/put_cpu.
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*/
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static int toggle_hw_mce_inject(unsigned int cpu, bool enable)
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{
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u32 l, h;
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int err;
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err = rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h);
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if (err) {
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pr_err("%s: error reading HWCR\n", __func__);
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return err;
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}
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enable ? (l |= BIT(18)) : (l &= ~BIT(18));
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err = wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h);
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if (err)
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pr_err("%s: error writing HWCR\n", __func__);
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return err;
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}
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static int __set_inj(const char *buf)
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{
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int i;
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for (i = 0; i < N_INJ_TYPES; i++) {
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if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) {
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inj_type = i;
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return 0;
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}
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}
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return -EINVAL;
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}
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static ssize_t flags_read(struct file *filp, char __user *ubuf,
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size_t cnt, loff_t *ppos)
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{
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char buf[MAX_FLAG_OPT_SIZE];
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int n;
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n = sprintf(buf, "%s\n", flags_options[inj_type]);
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return simple_read_from_buffer(ubuf, cnt, ppos, buf, n);
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}
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static ssize_t flags_write(struct file *filp, const char __user *ubuf,
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size_t cnt, loff_t *ppos)
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{
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char buf[MAX_FLAG_OPT_SIZE], *__buf;
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int err;
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size_t ret;
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if (cnt > MAX_FLAG_OPT_SIZE)
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cnt = MAX_FLAG_OPT_SIZE;
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ret = cnt;
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if (copy_from_user(&buf, ubuf, cnt))
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return -EFAULT;
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buf[cnt - 1] = 0;
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/* strip whitespace */
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__buf = strstrip(buf);
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err = __set_inj(__buf);
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if (err) {
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pr_err("%s: Invalid flags value: %s\n", __func__, __buf);
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return err;
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}
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*ppos += ret;
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return ret;
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}
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static const struct file_operations flags_fops = {
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.read = flags_read,
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.write = flags_write,
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.llseek = generic_file_llseek,
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};
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/*
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* On which CPU to inject?
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*/
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MCE_INJECT_GET(extcpu);
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static int inj_extcpu_set(void *data, u64 val)
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{
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struct mce *m = (struct mce *)data;
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if (val >= nr_cpu_ids || !cpu_online(val)) {
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pr_err("%s: Invalid CPU: %llu\n", __func__, val);
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return -EINVAL;
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}
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m->extcpu = val;
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return 0;
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}
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DEFINE_SIMPLE_ATTRIBUTE(extcpu_fops, inj_extcpu_get, inj_extcpu_set, "%llu\n");
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static void trigger_mce(void *info)
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{
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asm volatile("int $18");
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}
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static void do_inject(void)
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{
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u64 mcg_status = 0;
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unsigned int cpu = i_mce.extcpu;
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u8 b = i_mce.bank;
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if (i_mce.misc)
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i_mce.status |= MCI_STATUS_MISCV;
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if (inj_type == SW_INJ) {
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amd_decode_mce(NULL, 0, &i_mce);
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return;
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}
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/* prep MCE global settings for the injection */
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mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV;
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if (!(i_mce.status & MCI_STATUS_PCC))
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mcg_status |= MCG_STATUS_RIPV;
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get_online_cpus();
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if (!cpu_online(cpu))
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goto err;
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toggle_hw_mce_inject(cpu, true);
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wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS,
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(u32)mcg_status, (u32)(mcg_status >> 32));
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wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b),
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(u32)i_mce.status, (u32)(i_mce.status >> 32));
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wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b),
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(u32)i_mce.addr, (u32)(i_mce.addr >> 32));
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wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b),
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(u32)i_mce.misc, (u32)(i_mce.misc >> 32));
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toggle_hw_mce_inject(cpu, false);
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smp_call_function_single(cpu, trigger_mce, NULL, 0);
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err:
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put_online_cpus();
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}
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/*
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* This denotes into which bank we're injecting and triggers
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* the injection, at the same time.
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*/
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static int inj_bank_set(void *data, u64 val)
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{
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struct mce *m = (struct mce *)data;
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if (val >= n_banks) {
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pr_err("Non-existent MCE bank: %llu\n", val);
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return -EINVAL;
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}
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m->bank = val;
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do_inject();
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return 0;
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}
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MCE_INJECT_GET(bank);
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DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n");
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static const char readme_msg[] =
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"Description of the files and their usages:\n"
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"\n"
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"Note1: i refers to the bank number below.\n"
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"Note2: See respective BKDGs for the exact bit definitions of the files below\n"
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"as they mirror the hardware registers.\n"
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"\n"
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"status:\t Set MCi_STATUS: the bits in that MSR control the error type and\n"
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"\t attributes of the error which caused the MCE.\n"
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"\n"
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"misc:\t Set MCi_MISC: provide auxiliary info about the error. It is mostly\n"
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"\t used for error thresholding purposes and its validity is indicated by\n"
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"\t MCi_STATUS[MiscV].\n"
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"\n"
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"addr:\t Error address value to be written to MCi_ADDR. Log address information\n"
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"\t associated with the error.\n"
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"\n"
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"cpu:\t The CPU to inject the error on.\n"
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"\n"
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"bank:\t Specify the bank you want to inject the error into: the number of\n"
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"\t banks in a processor varies and is family/model-specific, therefore, the\n"
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"\t supplied value is sanity-checked. Setting the bank value also triggers the\n"
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"\t injection.\n"
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"\n"
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"flags:\t Injection type to be performed. Writing to this file will trigger a\n"
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"\t real machine check, an APIC interrupt or invoke the error decoder routines\n"
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"\t for AMD processors.\n"
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"\n"
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"\t Allowed error injection types:\n"
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"\t - \"sw\": Software error injection. Decode error to a human-readable \n"
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"\t format only. Safe to use.\n"
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"\t - \"hw\": Hardware error injection. Causes the #MC exception handler to \n"
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"\t handle the error. Be warned: might cause system panic if MCi_STATUS[PCC] \n"
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"\t is set. Therefore, consider setting (debugfs_mountpoint)/mce/fake_panic \n"
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"\t before injecting.\n"
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"\n";
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static ssize_t
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inj_readme_read(struct file *filp, char __user *ubuf,
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size_t cnt, loff_t *ppos)
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{
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return simple_read_from_buffer(ubuf, cnt, ppos,
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readme_msg, strlen(readme_msg));
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}
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static const struct file_operations readme_fops = {
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.read = inj_readme_read,
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};
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static struct dfs_node {
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char *name;
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struct dentry *d;
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const struct file_operations *fops;
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umode_t perm;
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} dfs_fls[] = {
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{ .name = "status", .fops = &status_fops, .perm = S_IRUSR | S_IWUSR },
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{ .name = "misc", .fops = &misc_fops, .perm = S_IRUSR | S_IWUSR },
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{ .name = "addr", .fops = &addr_fops, .perm = S_IRUSR | S_IWUSR },
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{ .name = "bank", .fops = &bank_fops, .perm = S_IRUSR | S_IWUSR },
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{ .name = "flags", .fops = &flags_fops, .perm = S_IRUSR | S_IWUSR },
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{ .name = "cpu", .fops = &extcpu_fops, .perm = S_IRUSR | S_IWUSR },
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{ .name = "README", .fops = &readme_fops, .perm = S_IRUSR | S_IRGRP | S_IROTH },
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};
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static int __init init_mce_inject(void)
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{
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int i;
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u64 cap;
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rdmsrl(MSR_IA32_MCG_CAP, cap);
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n_banks = cap & MCG_BANKCNT_MASK;
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dfs_inj = debugfs_create_dir("mce-inject", NULL);
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if (!dfs_inj)
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return -EINVAL;
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for (i = 0; i < ARRAY_SIZE(dfs_fls); i++) {
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dfs_fls[i].d = debugfs_create_file(dfs_fls[i].name,
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dfs_fls[i].perm,
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dfs_inj,
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&i_mce,
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dfs_fls[i].fops);
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if (!dfs_fls[i].d)
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goto err_dfs_add;
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}
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return 0;
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err_dfs_add:
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while (--i >= 0)
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debugfs_remove(dfs_fls[i].d);
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debugfs_remove(dfs_inj);
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dfs_inj = NULL;
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return -ENOMEM;
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}
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static void __exit exit_mce_inject(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(dfs_fls); i++)
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debugfs_remove(dfs_fls[i].d);
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memset(&dfs_fls, 0, sizeof(dfs_fls));
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debugfs_remove(dfs_inj);
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dfs_inj = NULL;
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}
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module_init(init_mce_inject);
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module_exit(exit_mce_inject);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Borislav Petkov <bp@alien8.de>");
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MODULE_AUTHOR("AMD Inc.");
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MODULE_DESCRIPTION("MCE injection facility for RAS testing");
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Reference in New Issue
Block a user