Merge branch 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull RAS updates from Ingo Molnar: "MCE handling updates, but also some generic drivers/edac/ changes to better organize the Kconfig space" * 'ras-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/ras: Move AMD MCE injector to arch/x86/ras/ x86/mce: Add a wrapper around mce_log() for injection x86/mce: Rename rcu_dereference_check_mce() to mce_log_get_idx_check() RAS: Add a menuconfig option with descriptive text x86/mce: Reenable CMCI banks when swiching back to interrupt mode x86/mce: Clear Local MCE opt-in before kexec x86/mce: Remove unused function declarations x86/mce: Kill drain_mcelog_buffer() x86/mce: Avoid potential deadlock due to printk() in MCE context x86/mce: Remove the MCE ring for Action Optional errors x86/mce: Don't use percpu workqueues x86/mce: Provide a lockless memory pool to save error records x86/mce: Reuse one of the u16 padding fields in 'struct mce'
This commit is contained in:
Linus Torvalds
@@ -52,11 +52,11 @@
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static DEFINE_MUTEX(mce_chrdev_read_mutex);
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#define rcu_dereference_check_mce(p) \
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#define mce_log_get_idx_check(p) \
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({ \
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RCU_LOCKDEP_WARN(!rcu_read_lock_sched_held() && \
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!lockdep_is_held(&mce_chrdev_read_mutex), \
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"suspicious rcu_dereference_check_mce() usage"); \
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"suspicious mce_log_get_idx_check() usage"); \
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smp_load_acquire(&(p)); \
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})
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@@ -110,15 +110,17 @@ DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
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*/
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mce_banks_t mce_banks_ce_disabled;
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static DEFINE_PER_CPU(struct work_struct, mce_work);
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static struct work_struct mce_work;
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static struct irq_work mce_irq_work;
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static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
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static int mce_usable_address(struct mce *m);
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/*
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* CPU/chipset specific EDAC code can register a notifier call here to print
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* MCE errors in a human-readable form.
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*/
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static ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
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ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
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/* Do initial initialization of a struct mce */
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void mce_setup(struct mce *m)
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@@ -157,12 +159,13 @@ void mce_log(struct mce *mce)
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/* Emit the trace record: */
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trace_mce_record(mce);
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atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
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if (!mce_gen_pool_add(mce))
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irq_work_queue(&mce_irq_work);
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mce->finished = 0;
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wmb();
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for (;;) {
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entry = rcu_dereference_check_mce(mcelog.next);
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entry = mce_log_get_idx_check(mcelog.next);
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for (;;) {
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/*
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@@ -196,48 +199,23 @@ void mce_log(struct mce *mce)
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set_bit(0, &mce_need_notify);
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}
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static void drain_mcelog_buffer(void)
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void mce_inject_log(struct mce *m)
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{
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unsigned int next, i, prev = 0;
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next = ACCESS_ONCE(mcelog.next);
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do {
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struct mce *m;
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/* drain what was logged during boot */
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for (i = prev; i < next; i++) {
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unsigned long start = jiffies;
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unsigned retries = 1;
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m = &mcelog.entry[i];
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while (!m->finished) {
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if (time_after_eq(jiffies, start + 2*retries))
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retries++;
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cpu_relax();
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if (!m->finished && retries >= 4) {
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pr_err("skipping error being logged currently!\n");
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break;
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}
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}
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smp_rmb();
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atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
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}
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memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m));
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prev = next;
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next = cmpxchg(&mcelog.next, prev, 0);
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} while (next != prev);
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mutex_lock(&mce_chrdev_read_mutex);
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mce_log(m);
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mutex_unlock(&mce_chrdev_read_mutex);
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}
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EXPORT_SYMBOL_GPL(mce_inject_log);
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static struct notifier_block mce_srao_nb;
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void mce_register_decode_chain(struct notifier_block *nb)
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{
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/* Ensure SRAO notifier has the highest priority in the decode chain. */
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if (nb != &mce_srao_nb && nb->priority == INT_MAX)
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nb->priority -= 1;
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atomic_notifier_chain_register(&x86_mce_decoder_chain, nb);
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drain_mcelog_buffer();
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}
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EXPORT_SYMBOL_GPL(mce_register_decode_chain);
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@@ -461,61 +439,6 @@ static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
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}
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}
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/*
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* Simple lockless ring to communicate PFNs from the exception handler with the
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* process context work function. This is vastly simplified because there's
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* only a single reader and a single writer.
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*/
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#define MCE_RING_SIZE 16 /* we use one entry less */
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struct mce_ring {
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unsigned short start;
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unsigned short end;
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unsigned long ring[MCE_RING_SIZE];
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};
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static DEFINE_PER_CPU(struct mce_ring, mce_ring);
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/* Runs with CPU affinity in workqueue */
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static int mce_ring_empty(void)
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{
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struct mce_ring *r = this_cpu_ptr(&mce_ring);
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return r->start == r->end;
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}
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static int mce_ring_get(unsigned long *pfn)
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{
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struct mce_ring *r;
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int ret = 0;
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*pfn = 0;
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get_cpu();
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r = this_cpu_ptr(&mce_ring);
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if (r->start == r->end)
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goto out;
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*pfn = r->ring[r->start];
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r->start = (r->start + 1) % MCE_RING_SIZE;
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ret = 1;
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out:
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put_cpu();
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return ret;
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}
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/* Always runs in MCE context with preempt off */
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static int mce_ring_add(unsigned long pfn)
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{
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struct mce_ring *r = this_cpu_ptr(&mce_ring);
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unsigned next;
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next = (r->end + 1) % MCE_RING_SIZE;
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if (next == r->start)
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return -1;
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r->ring[r->end] = pfn;
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wmb();
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r->end = next;
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return 0;
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}
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int mce_available(struct cpuinfo_x86 *c)
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{
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if (mca_cfg.disabled)
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@@ -525,12 +448,10 @@ int mce_available(struct cpuinfo_x86 *c)
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static void mce_schedule_work(void)
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{
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if (!mce_ring_empty())
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schedule_work(this_cpu_ptr(&mce_work));
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if (!mce_gen_pool_empty() && keventd_up())
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schedule_work(&mce_work);
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}
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static DEFINE_PER_CPU(struct irq_work, mce_irq_work);
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static void mce_irq_work_cb(struct irq_work *entry)
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{
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mce_notify_irq();
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@@ -551,9 +472,30 @@ static void mce_report_event(struct pt_regs *regs)
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return;
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}
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irq_work_queue(this_cpu_ptr(&mce_irq_work));
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irq_work_queue(&mce_irq_work);
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}
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static int srao_decode_notifier(struct notifier_block *nb, unsigned long val,
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void *data)
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{
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struct mce *mce = (struct mce *)data;
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unsigned long pfn;
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if (!mce)
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return NOTIFY_DONE;
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if (mce->usable_addr && (mce->severity == MCE_AO_SEVERITY)) {
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pfn = mce->addr >> PAGE_SHIFT;
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memory_failure(pfn, MCE_VECTOR, 0);
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}
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return NOTIFY_OK;
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}
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static struct notifier_block mce_srao_nb = {
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.notifier_call = srao_decode_notifier,
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.priority = INT_MAX,
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};
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/*
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* Read ADDR and MISC registers.
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*/
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@@ -672,8 +614,11 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
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*/
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if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) {
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if (m.status & MCI_STATUS_ADDRV) {
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mce_ring_add(m.addr >> PAGE_SHIFT);
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mce_schedule_work();
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m.severity = severity;
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m.usable_addr = mce_usable_address(&m);
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if (!mce_gen_pool_add(&m))
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mce_schedule_work();
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}
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}
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@@ -1143,15 +1088,9 @@ void do_machine_check(struct pt_regs *regs, long error_code)
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mce_read_aux(&m, i);
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/*
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* Action optional error. Queue address for later processing.
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* When the ring overflows we just ignore the AO error.
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* RED-PEN add some logging mechanism when
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* usable_address or mce_add_ring fails.
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* RED-PEN don't ignore overflow for mca_cfg.tolerant == 0
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*/
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if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
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mce_ring_add(m.addr >> PAGE_SHIFT);
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/* assuming valid severity level != 0 */
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m.severity = severity;
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m.usable_addr = mce_usable_address(&m);
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mce_log(&m);
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@@ -1247,14 +1186,11 @@ int memory_failure(unsigned long pfn, int vector, int flags)
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/*
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* Action optional processing happens here (picking up
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* from the list of faulting pages that do_machine_check()
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* placed into the "ring").
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* placed into the genpool).
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*/
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static void mce_process_work(struct work_struct *dummy)
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{
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unsigned long pfn;
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while (mce_ring_get(&pfn))
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memory_failure(pfn, MCE_VECTOR, 0);
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mce_gen_pool_process();
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}
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#ifdef CONFIG_X86_MCE_INTEL
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@@ -1678,6 +1614,17 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
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}
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}
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static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c)
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{
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switch (c->x86_vendor) {
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case X86_VENDOR_INTEL:
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mce_intel_feature_clear(c);
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break;
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default:
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break;
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}
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}
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static void mce_start_timer(unsigned int cpu, struct timer_list *t)
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{
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unsigned long iv = check_interval * HZ;
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@@ -1731,13 +1678,36 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
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return;
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}
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if (mce_gen_pool_init()) {
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mca_cfg.disabled = true;
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pr_emerg("Couldn't allocate MCE records pool!\n");
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return;
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}
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machine_check_vector = do_machine_check;
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__mcheck_cpu_init_generic();
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__mcheck_cpu_init_vendor(c);
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__mcheck_cpu_init_timer();
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INIT_WORK(this_cpu_ptr(&mce_work), mce_process_work);
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init_irq_work(this_cpu_ptr(&mce_irq_work), &mce_irq_work_cb);
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}
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/*
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* Called for each booted CPU to clear some machine checks opt-ins
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*/
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void mcheck_cpu_clear(struct cpuinfo_x86 *c)
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{
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if (mca_cfg.disabled)
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return;
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if (!mce_available(c))
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return;
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/*
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* Possibly to clear general settings generic to x86
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* __mcheck_cpu_clear_generic(c);
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*/
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__mcheck_cpu_clear_vendor(c);
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}
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/*
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@@ -1850,7 +1820,7 @@ static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
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goto out;
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}
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next = rcu_dereference_check_mce(mcelog.next);
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next = mce_log_get_idx_check(mcelog.next);
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/* Only supports full reads right now */
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err = -EINVAL;
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@@ -2056,8 +2026,12 @@ __setup("mce", mcheck_enable);
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int __init mcheck_init(void)
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{
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mcheck_intel_therm_init();
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mce_register_decode_chain(&mce_srao_nb);
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mcheck_vendor_init_severity();
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INIT_WORK(&mce_work, mce_process_work);
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init_irq_work(&mce_irq_work, mce_irq_work_cb);
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return 0;
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}
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@@ -2591,5 +2565,20 @@ static int __init mcheck_debugfs_init(void)
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return 0;
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}
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late_initcall(mcheck_debugfs_init);
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#else
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static int __init mcheck_debugfs_init(void) { return -EINVAL; }
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#endif
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static int __init mcheck_late_init(void)
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{
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mcheck_debugfs_init();
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/*
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* Flush out everything that has been logged during early boot, now that
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* everything has been initialized (workqueues, decoders, ...).
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*/
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mce_schedule_work();
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return 0;
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}
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late_initcall(mcheck_late_init);
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