drm/i915/ehl: Inherit Ice Lake conditional code
Most of the conditional code for ICELAKE also applies to ELKHARTLAKE so use IS_GEN(dev_priv, 11) even for PM and Workarounds for now. v2: - Rename commit (Jose) - Include a wm workaround (Jose and Lucas) - Include display core init (Jose and Lucas) v3: Add a missing case of gen greater-than 11 (Jose) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190412180920.22347-1-rodrigo.vivi@intel.com
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@@ -4530,10 +4530,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
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memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
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/*
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* Wa_1408961008:icl
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* Wa_1408961008:icl, ehl
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* Underruns with WM1+ disabled
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*/
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if (IS_ICELAKE(dev_priv) &&
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if (IS_GEN(dev_priv, 11) &&
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level == 1 && wm->wm[0].plane_en) {
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wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
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wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
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@@ -9573,7 +9573,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
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*/
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void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
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{
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if (IS_ICELAKE(dev_priv))
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if (IS_GEN(dev_priv, 11))
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dev_priv->display.init_clock_gating = icl_init_clock_gating;
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else if (IS_CANNONLAKE(dev_priv))
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dev_priv->display.init_clock_gating = cnl_init_clock_gating;
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