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MIPS: Malta: Probe interrupt controllers via DT

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Probe the CPU, GIC & i8259 interrupt controllers present in the Malta
system using device tree. This enables interrupts to be provided to
devices using device tree as they are moved over to being probed using
it.

Since Malta is very configurable it's unknown whether a GIC will be
present at compile time. In order to support both cases the
malta_dt_shim code is added in order to detect whether a GIC is present,
adjusting the DT to route interrupts correctly and nop out the GIC node
if no GIC is found.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14274/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
2016-09-19 22:21:23 +01:00
committed by Ralf Baechle
parent 0051fc2e7b
commit 38ec82fe21
4 changed files with 124 additions and 91 deletions
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41
arch/mips/boot/dts/mti/malta.dts
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@@ -1,5 +1,8 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/mips-gic.h>
/memreserve/ 0x00000000 0x00001000; /* YAMON exception vectors */
/memreserve/ 0x00001000 0x000ef000; /* YAMON */
/memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */
@@ -8,4 +11,42 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "mti,malta";
cpu_intc: interrupt-controller {
compatible = "mti,cpu-interrupt-controller";
interrupt-controller;
#interrupt-cells = <1>;
};
gic: interrupt-controller@1bdc0000 {
compatible = "mti,gic";
reg = <0x1bdc0000 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
/*
* Declare the interrupt-parent even though the mti,gic
* binding doesn't require it, such that the kernel can
* figure out that cpu_intc is the root interrupt
* controller & should be probed first.
*/
interrupt-parent = <&cpu_intc>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
};
};
i8259: interrupt-controller@20 {
compatible = "intel,i8259";
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
};
};