amd-xgbe: Set DMA mask based on hardware register value
The hardware supplies a value that indicates the DMA range that it is capable of using. Use this value rather than hard-coding it in the driver. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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committed by
David S. Miller

parent
ceb8f6be7e
commit
386d325dbd
@@ -374,15 +374,6 @@ static int xgbe_probe(struct platform_device *pdev)
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pdata->awcache = XGBE_DMA_SYS_AWCACHE;
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}
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/* Set the DMA mask */
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if (!dev->dma_mask)
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dev->dma_mask = &dev->coherent_dma_mask;
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ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
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if (ret) {
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dev_err(dev, "dma_set_mask_and_coherent failed\n");
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goto err_io;
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}
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/* Get the device interrupt */
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ret = platform_get_irq(pdev, 0);
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if (ret < 0) {
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@@ -409,6 +400,16 @@ static int xgbe_probe(struct platform_device *pdev)
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/* Set default configuration data */
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xgbe_default_config(pdata);
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/* Set the DMA mask */
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if (!dev->dma_mask)
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dev->dma_mask = &dev->coherent_dma_mask;
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ret = dma_set_mask_and_coherent(dev,
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DMA_BIT_MASK(pdata->hw_feat.dma_width));
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if (ret) {
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dev_err(dev, "dma_set_mask_and_coherent failed\n");
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goto err_io;
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}
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/* Calculate the number of Tx and Rx rings to be created
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* -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
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* the number of Tx queues to the number of Tx channels
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