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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Browse Source 
Pull ARM SoC driver updates from Arnd Bergmann:
 "As usual, the drivers/tee and drivers/reset subsystems get merged
  here, with the expected set of smaller updates and some new hardware
  support. The tee subsystem now supports device drivers to be attached
  to a tee, the first example here is a random number driver with its
  implementation in the secure world.

  Three new power domain drivers get added for specific chip families:
   - Broadcom BCM283x chips (used in Raspberry Pi)
   - Qualcomm Snapdragon phone chips
   - Xilinx ZynqMP FPGA SoCs

  One new driver is added to talk to the BPMP firmware on NVIDIA
  Tegra210

  Existing drivers are extended for new SoC variants from NXP, NVIDIA,
  Amlogic and Qualcomm"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (113 commits)
  tee: optee: update optee_msg.h and optee_smc.h to dual license
  tee: add cancellation support to client interface
  dpaa2-eth: configure the cache stashing amount on a queue
  soc: fsl: dpio: configure cache stashing destination
  soc: fsl: dpio: enable frame data cache stashing per software portal
  soc: fsl: guts: make fsl_guts_get_svr() static
  hwrng: make symbol 'optee_rng_id_table' static
  tee: optee: Fix unsigned comparison with less than zero
  hwrng: Fix unsigned comparison with less than zero
  tee: fix possible error pointer ctx dereferencing
  hwrng: optee: Initialize some structs using memset instead of braces
  tee: optee: Initialize some structs using memset instead of braces
  soc: fsl: dpio: fix memory leak of a struct qbman on error exit path
  clk: tegra: dfll: Make symbol 'tegra210_cpu_cvb_tables' static
  soc: qcom: llcc-slice: Fix typos
  qcom: soc: llcc-slice: Consolidate some code
  qcom: soc: llcc-slice: Clear the global drv_data pointer on error
  drivers: soc: xilinx: Add ZynqMP power domain driver
  firmware: xilinx: Add APIs to control node status/power
  dt-bindings: power: Add ZynqMP power domain bindings
  ...
This commit is contained in:
Linus Torvalds
2019-03-06 09:41:12 -08:00
parent 6ad63dec9c 8ceb820b69
commit 384d11fa0e
126 changed files with 7125 additions and 747 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
include/linux/firmware/imx/svc/misc.h
View File

@@ -52,4 +52,7 @@ int imx_sc_misc_set_control(struct imx_sc_ipc *ipc, u32 resource,
int imx_sc_misc_get_control(struct imx_sc_ipc *ipc, u32 resource,
u8 ctrl, u32 *val);
int imx_sc_pm_cpu_start(struct imx_sc_ipc *ipc, u32 resource,
bool enable, u64 phys_addr);
#endif /* _SC_MISC_API_H */

184
include/linux/firmware/xlnx-zynqmp.h
View File

@@ -28,12 +28,35 @@
/* SMC SIP service Call Function Identifier Prefix */
#define PM_SIP_SVC 0xC2000000
#define PM_GET_TRUSTZONE_VERSION 0xa03
#define PM_SET_SUSPEND_MODE 0xa02
#define GET_CALLBACK_DATA 0xa01
/* Number of 32bits values in payload */
#define PAYLOAD_ARG_CNT 4U
/* Number of arguments for a callback */
#define CB_ARG_CNT 4
/* Payload size (consists of callback API ID + arguments) */
#define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
#define ZYNQMP_PM_MAX_QOS 100U
/* Node capabilities */
#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
#define ZYNQMP_PM_CAPABILITY_POWER 0x8U
enum pm_api_id {
PM_GET_API_VERSION = 1,
PM_REQUEST_NODE = 13,
PM_RELEASE_NODE,
PM_SET_REQUIREMENT,
PM_RESET_ASSERT = 17,
PM_RESET_GET_STATUS,
PM_PM_INIT_FINALIZE = 21,
PM_GET_CHIPID = 24,
PM_IOCTL = 34,
PM_QUERY_DATA,
PM_CLOCK_ENABLE,
@@ -75,6 +98,149 @@ enum pm_query_id {
PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
};
enum zynqmp_pm_reset_action {
PM_RESET_ACTION_RELEASE,
PM_RESET_ACTION_ASSERT,
PM_RESET_ACTION_PULSE,
};
enum zynqmp_pm_reset {
ZYNQMP_PM_RESET_START = 1000,
ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
ZYNQMP_PM_RESET_PCIE_BRIDGE,
ZYNQMP_PM_RESET_PCIE_CTRL,
ZYNQMP_PM_RESET_DP,
ZYNQMP_PM_RESET_SWDT_CRF,
ZYNQMP_PM_RESET_AFI_FM5,
ZYNQMP_PM_RESET_AFI_FM4,
ZYNQMP_PM_RESET_AFI_FM3,
ZYNQMP_PM_RESET_AFI_FM2,
ZYNQMP_PM_RESET_AFI_FM1,
ZYNQMP_PM_RESET_AFI_FM0,
ZYNQMP_PM_RESET_GDMA,
ZYNQMP_PM_RESET_GPU_PP1,
ZYNQMP_PM_RESET_GPU_PP0,
ZYNQMP_PM_RESET_GPU,
ZYNQMP_PM_RESET_GT,
ZYNQMP_PM_RESET_SATA,
ZYNQMP_PM_RESET_ACPU3_PWRON,
ZYNQMP_PM_RESET_ACPU2_PWRON,
ZYNQMP_PM_RESET_ACPU1_PWRON,
ZYNQMP_PM_RESET_ACPU0_PWRON,
ZYNQMP_PM_RESET_APU_L2,
ZYNQMP_PM_RESET_ACPU3,
ZYNQMP_PM_RESET_ACPU2,
ZYNQMP_PM_RESET_ACPU1,
ZYNQMP_PM_RESET_ACPU0,
ZYNQMP_PM_RESET_DDR,
ZYNQMP_PM_RESET_APM_FPD,
ZYNQMP_PM_RESET_SOFT,
ZYNQMP_PM_RESET_GEM0,
ZYNQMP_PM_RESET_GEM1,
ZYNQMP_PM_RESET_GEM2,
ZYNQMP_PM_RESET_GEM3,
ZYNQMP_PM_RESET_QSPI,
ZYNQMP_PM_RESET_UART0,
ZYNQMP_PM_RESET_UART1,
ZYNQMP_PM_RESET_SPI0,
ZYNQMP_PM_RESET_SPI1,
ZYNQMP_PM_RESET_SDIO0,
ZYNQMP_PM_RESET_SDIO1,
ZYNQMP_PM_RESET_CAN0,
ZYNQMP_PM_RESET_CAN1,
ZYNQMP_PM_RESET_I2C0,
ZYNQMP_PM_RESET_I2C1,
ZYNQMP_PM_RESET_TTC0,
ZYNQMP_PM_RESET_TTC1,
ZYNQMP_PM_RESET_TTC2,
ZYNQMP_PM_RESET_TTC3,
ZYNQMP_PM_RESET_SWDT_CRL,
ZYNQMP_PM_RESET_NAND,
ZYNQMP_PM_RESET_ADMA,
ZYNQMP_PM_RESET_GPIO,
ZYNQMP_PM_RESET_IOU_CC,
ZYNQMP_PM_RESET_TIMESTAMP,
ZYNQMP_PM_RESET_RPU_R50,
ZYNQMP_PM_RESET_RPU_R51,
ZYNQMP_PM_RESET_RPU_AMBA,
ZYNQMP_PM_RESET_OCM,
ZYNQMP_PM_RESET_RPU_PGE,
ZYNQMP_PM_RESET_USB0_CORERESET,
ZYNQMP_PM_RESET_USB1_CORERESET,
ZYNQMP_PM_RESET_USB0_HIBERRESET,
ZYNQMP_PM_RESET_USB1_HIBERRESET,
ZYNQMP_PM_RESET_USB0_APB,
ZYNQMP_PM_RESET_USB1_APB,
ZYNQMP_PM_RESET_IPI,
ZYNQMP_PM_RESET_APM_LPD,
ZYNQMP_PM_RESET_RTC,
ZYNQMP_PM_RESET_SYSMON,
ZYNQMP_PM_RESET_AFI_FM6,
ZYNQMP_PM_RESET_LPD_SWDT,
ZYNQMP_PM_RESET_FPD,
ZYNQMP_PM_RESET_RPU_DBG1,
ZYNQMP_PM_RESET_RPU_DBG0,
ZYNQMP_PM_RESET_DBG_LPD,
ZYNQMP_PM_RESET_DBG_FPD,
ZYNQMP_PM_RESET_APLL,
ZYNQMP_PM_RESET_DPLL,
ZYNQMP_PM_RESET_VPLL,
ZYNQMP_PM_RESET_IOPLL,
ZYNQMP_PM_RESET_RPLL,
ZYNQMP_PM_RESET_GPO3_PL_0,
ZYNQMP_PM_RESET_GPO3_PL_1,
ZYNQMP_PM_RESET_GPO3_PL_2,
ZYNQMP_PM_RESET_GPO3_PL_3,
ZYNQMP_PM_RESET_GPO3_PL_4,
ZYNQMP_PM_RESET_GPO3_PL_5,
ZYNQMP_PM_RESET_GPO3_PL_6,
ZYNQMP_PM_RESET_GPO3_PL_7,
ZYNQMP_PM_RESET_GPO3_PL_8,
ZYNQMP_PM_RESET_GPO3_PL_9,
ZYNQMP_PM_RESET_GPO3_PL_10,
ZYNQMP_PM_RESET_GPO3_PL_11,
ZYNQMP_PM_RESET_GPO3_PL_12,
ZYNQMP_PM_RESET_GPO3_PL_13,
ZYNQMP_PM_RESET_GPO3_PL_14,
ZYNQMP_PM_RESET_GPO3_PL_15,
ZYNQMP_PM_RESET_GPO3_PL_16,
ZYNQMP_PM_RESET_GPO3_PL_17,
ZYNQMP_PM_RESET_GPO3_PL_18,
ZYNQMP_PM_RESET_GPO3_PL_19,
ZYNQMP_PM_RESET_GPO3_PL_20,
ZYNQMP_PM_RESET_GPO3_PL_21,
ZYNQMP_PM_RESET_GPO3_PL_22,
ZYNQMP_PM_RESET_GPO3_PL_23,
ZYNQMP_PM_RESET_GPO3_PL_24,
ZYNQMP_PM_RESET_GPO3_PL_25,
ZYNQMP_PM_RESET_GPO3_PL_26,
ZYNQMP_PM_RESET_GPO3_PL_27,
ZYNQMP_PM_RESET_GPO3_PL_28,
ZYNQMP_PM_RESET_GPO3_PL_29,
ZYNQMP_PM_RESET_GPO3_PL_30,
ZYNQMP_PM_RESET_GPO3_PL_31,
ZYNQMP_PM_RESET_RPU_LS,
ZYNQMP_PM_RESET_PS_ONLY,
ZYNQMP_PM_RESET_PL,
ZYNQMP_PM_RESET_PS_PL0,
ZYNQMP_PM_RESET_PS_PL1,
ZYNQMP_PM_RESET_PS_PL2,
ZYNQMP_PM_RESET_PS_PL3,
ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
};
enum zynqmp_pm_suspend_reason {
SUSPEND_POWER_REQUEST = 201,
SUSPEND_ALERT,
SUSPEND_SYSTEM_SHUTDOWN,
};
enum zynqmp_pm_request_ack {
ZYNQMP_PM_REQUEST_ACK_NO = 1,
ZYNQMP_PM_REQUEST_ACK_BLOCKING,
ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
};
/**
* struct zynqmp_pm_query_data - PM query data
* @qid: query ID
@@ -91,6 +257,7 @@ struct zynqmp_pm_query_data {
struct zynqmp_eemi_ops {
int (*get_api_version)(u32 *version);
int (*get_chipid)(u32 *idcode, u32 *version);
int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
int (*clock_enable)(u32 clock_id);
int (*clock_disable)(u32 clock_id);
@@ -102,8 +269,25 @@ struct zynqmp_eemi_ops {
int (*clock_setparent)(u32 clock_id, u32 parent_id);
int (*clock_getparent)(u32 clock_id, u32 *parent_id);
int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
int (*reset_assert)(const enum zynqmp_pm_reset reset,
const enum zynqmp_pm_reset_action assert_flag);
int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status);
int (*init_finalize)(void);
int (*set_suspend_mode)(u32 mode);
int (*request_node)(const u32 node,
const u32 capabilities,
const u32 qos,
const enum zynqmp_pm_request_ack ack);
int (*release_node)(const u32 node);
int (*set_requirement)(const u32 node,
const u32 capabilities,
const u32 qos,
const enum zynqmp_pm_request_ack ack);
};
int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
u32 arg2, u32 arg3, u32 *ret_payload);
#if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
#else

2
include/linux/fsl/guts.h
View File

@@ -135,8 +135,6 @@ struct ccsr_guts {
u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));
u32 fsl_guts_get_svr(void);
/* Alternate function signal multiplex control */
#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))

14
include/linux/mfd/bcm2835-pm.h Normal file
View File

@@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef BCM2835_MFD_PM_H
#define BCM2835_MFD_PM_H
#include <linux/regmap.h>
struct bcm2835_pm {
struct device *dev;
void __iomem *base;
void __iomem *asb;
};
#endif /* BCM2835_MFD_PM_H */

9
include/linux/mod_devicetable.h
View File

@@ -779,4 +779,13 @@ struct typec_device_id {
kernel_ulong_t driver_data;
};
/**
* struct tee_client_device_id - tee based device identifier
* @uuid: For TEE based client devices we use the device uuid as
* the identifier.
*/
struct tee_client_device_id {
uuid_t uuid;
};
#endif /* LINUX_MOD_DEVICETABLE_H */

7
include/linux/pm_opp.h
View File

@@ -86,6 +86,8 @@ unsigned long dev_pm_opp_get_voltage(struct dev_pm_opp *opp);
unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp);
unsigned int dev_pm_opp_get_level(struct dev_pm_opp *opp);
bool dev_pm_opp_is_turbo(struct dev_pm_opp *opp);
int dev_pm_opp_get_opp_count(struct device *dev);
@@ -158,6 +160,11 @@ static inline unsigned long dev_pm_opp_get_freq(struct dev_pm_opp *opp)
return 0;
}
static inline unsigned int dev_pm_opp_get_level(struct dev_pm_opp *opp)
{
return 0;
}
static inline bool dev_pm_opp_is_turbo(struct dev_pm_opp *opp)
{
return false;

7
include/linux/reset/socfpga.h Normal file
View File

@@ -0,0 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LINUX_RESET_SOCFPGA_H__
#define __LINUX_RESET_SOCFPGA_H__
void __init socfpga_reset_init(void);
#endif /* __LINUX_RESET_SOCFPGA_H__ */

7
include/linux/reset/sunxi.h Normal file
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@@ -0,0 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __LINUX_RESET_SUNXI_H__
#define __LINUX_RESET_SUNXI_H__
void __init sun6i_reset_init(void);
#endif /* __LINUX_RESET_SUNXI_H__ */

6
include/linux/soc/qcom/llcc-qcom.h
View File

@@ -162,6 +162,12 @@ int llcc_slice_deactivate(struct llcc_slice_desc *desc);
*/
int qcom_llcc_probe(struct platform_device *pdev,
const struct llcc_slice_config *table, u32 sz);
/**
* qcom_llcc_remove - remove the sct table
* @pdev: Platform device pointer
*/
int qcom_llcc_remove(struct platform_device *pdev);
#else
static inline struct llcc_slice_desc *llcc_slice_getd(u32 uid)
{

50
include/linux/tee_drv.h
View File

@@ -15,11 +15,14 @@
#ifndef __TEE_DRV_H
#define __TEE_DRV_H
#include <linux/types.h>
#include <linux/device.h>
#include <linux/idr.h>
#include <linux/kref.h>
#include <linux/list.h>
#include <linux/mod_devicetable.h>
#include <linux/tee.h>
#include <linux/types.h>
#include <linux/uuid.h>
/*
* The file describes the API provided by the generic TEE driver to the
@@ -47,6 +50,11 @@ struct tee_shm_pool;
* @releasing: flag that indicates if context is being released right now.
* It is needed to break circular dependency on context during
* shared memory release.
* @supp_nowait: flag that indicates that requests in this context should not
* wait for tee-supplicant daemon to be started if not present
* and just return with an error code. It is needed for requests
* that arises from TEE based kernel drivers that should be
* non-blocking in nature.
*/
struct tee_context {
struct tee_device *teedev;
@@ -54,6 +62,7 @@ struct tee_context {
void *data;
struct kref refcount;
bool releasing;
bool supp_nowait;
};
struct tee_param_memref {
@@ -526,6 +535,18 @@ int tee_client_invoke_func(struct tee_context *ctx,
struct tee_ioctl_invoke_arg *arg,
struct tee_param *param);
/**
* tee_client_cancel_req() - Request cancellation of the previous open-session
* or invoke-command operations in a Trusted Application
* @ctx: TEE Context
* @arg: Cancellation arguments, see description of
* struct tee_ioctl_cancel_arg
*
* Returns < 0 on error else 0 if the cancellation was successfully requested.
*/
int tee_client_cancel_req(struct tee_context *ctx,
struct tee_ioctl_cancel_arg *arg);
static inline bool tee_param_is_memref(struct tee_param *param)
{
switch (param->attr & TEE_IOCTL_PARAM_ATTR_TYPE_MASK) {
@@ -538,4 +559,31 @@ static inline bool tee_param_is_memref(struct tee_param *param)
}
}
extern struct bus_type tee_bus_type;
/**
* struct tee_client_device - tee based device
* @id: device identifier
* @dev: device structure
*/
struct tee_client_device {
struct tee_client_device_id id;
struct device dev;
};
#define to_tee_client_device(d) container_of(d, struct tee_client_device, dev)
/**
* struct tee_client_driver - tee client driver
* @id_table: device id table supported by this driver
* @driver: driver structure
*/
struct tee_client_driver {
const struct tee_client_device_id *id_table;
struct device_driver driver;
};
#define to_tee_client_driver(d) \
container_of(d, struct tee_client_driver, driver)
#endif /*__TEE_DRV_H*/