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MIPS: Move headfiles to new location below arch/mips/include

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2008-09-16 19:48:51 +02:00
parent e8c7c48234
commit 384740dc49
463 changed files with 82 additions and 82 deletions
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43
arch/mips/include/asm/mach-dec/mc146818rtc.h Normal file
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/*
* RTC definitions for DECstation style attached Dallas DS1287 chip.
*
* Copyright (C) 1998, 2001 by Ralf Baechle
* Copyright (C) 1998 by Harald Koerfgen
* Copyright (C) 2002, 2005 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MIPS_DEC_RTC_DEC_H
#define __ASM_MIPS_DEC_RTC_DEC_H
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/dec/system.h>
extern volatile u8 *dec_rtc_base;
#define ARCH_RTC_LOCATION
#define RTC_PORT(x) CPHYSADDR((long)dec_rtc_base)
#define RTC_IO_EXTENT dec_kn_slot_size
#define RTC_IOMAPPED 0
#undef RTC_IRQ
#define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */
static inline unsigned char CMOS_READ(unsigned long addr)
{
return dec_rtc_base[addr * 4];
}
static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
{
dec_rtc_base[addr * 4] = data;
}
#define RTC_ALWAYS_BCD 0
#endif /* __ASM_MIPS_DEC_RTC_DEC_H */

25
arch/mips/include/asm/mach-dec/war.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_DEC_WAR_H
#define __ASM_MIPS_MACH_DEC_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define RM9000_CDEX_SMP_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_DEC_WAR_H */