xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

PCI: Hide pci_reset_bridge_secondary_bus() from drivers

Browse Source 
Rename pci_reset_bridge_secondary_bus() to pci_bridge_secondary_bus_reset()
and move the declaration from linux/pci.h to drivers/pci.h to be used
internally in PCI directory only.

Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Sinan Kaya
2018-07-19 18:04:11 -05:00
committed by Bjorn Helgaas
parent 409888e096
commit 381634cad1
6 changed files with 9 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/pci/hotplug/pciehp_hpc.c
View File

@@ -746,7 +746,7 @@ int pciehp_reset_slot(struct slot *slot, int probe)
if (pciehp_poll_mode) if (pciehp_poll_mode)
del_timer_sync(&ctrl->poll_timer); del_timer_sync(&ctrl->poll_timer);
rc = pci_reset_bridge_secondary_bus(ctrl->pcie->port); rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask); pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask); pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);

11
drivers/pci/pci.c
View File

@@ -4224,19 +4224,18 @@ void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
} }
/** /**
* pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge. * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
* @dev: Bridge device * @dev: Bridge device
* *
* Use the bridge control register to assert reset on the secondary bus. * Use the bridge control register to assert reset on the secondary bus.
* Devices on the secondary bus are left in power-on state. * Devices on the secondary bus are left in power-on state.
*/ */
int pci_reset_bridge_secondary_bus(struct pci_dev *dev) int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
{ {
pcibios_reset_secondary_bus(dev); pcibios_reset_secondary_bus(dev);
return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS); return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
} }
EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
static int pci_parent_bus_reset(struct pci_dev *dev, int probe) static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
{ {
@@ -4253,7 +4252,7 @@ static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
if (probe) if (probe)
return 0; return 0;
return pci_reset_bridge_secondary_bus(dev->bus->self); return pci_bridge_secondary_bus_reset(dev->bus->self);
} }
static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe) static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
@@ -4860,7 +4859,7 @@ static int pci_bus_reset(struct pci_bus *bus, int probe)
might_sleep(); might_sleep();
ret = pci_reset_bridge_secondary_bus(bus->self); ret = pci_bridge_secondary_bus_reset(bus->self);
pci_bus_unlock(bus); pci_bus_unlock(bus);
@@ -4924,7 +4923,7 @@ int pci_try_reset_bus(struct pci_bus *bus)
if (pci_bus_trylock(bus)) { if (pci_bus_trylock(bus)) {
might_sleep(); might_sleep();
rc = pci_reset_bridge_secondary_bus(bus->self); rc = pci_bridge_secondary_bus_reset(bus->self);
pci_bus_unlock(bus); pci_bus_unlock(bus);
} else } else
rc = -EAGAIN; rc = -EAGAIN;

1
drivers/pci/pci.h
View File

@@ -33,6 +33,7 @@ int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
enum pci_mmap_api mmap_api); enum pci_mmap_api mmap_api);
int pci_probe_reset_function(struct pci_dev *dev); int pci_probe_reset_function(struct pci_dev *dev);
int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
/** /**
* struct pci_platform_pm_ops - Firmware PM callbacks * struct pci_platform_pm_ops - Firmware PM callbacks

2
drivers/pci/pcie/aer.c
View File

@@ -1314,7 +1314,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK; reg32 &= ~ROOT_PORT_INTR_ON_MESG_MASK;
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32); pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
rc = pci_reset_bridge_secondary_bus(dev); rc = pci_bridge_secondary_bus_reset(dev);
pci_printk(KERN_DEBUG, dev, "Root Port link has been reset\n"); pci_printk(KERN_DEBUG, dev, "Root Port link has been reset\n");
/* Clear Root Error Status */ /* Clear Root Error Status */

2
drivers/pci/pcie/err.c
View File

@@ -177,7 +177,7 @@ static pci_ers_result_t default_reset_link(struct pci_dev *dev)
{ {
int rc; int rc;
rc = pci_reset_bridge_secondary_bus(dev); rc = pci_bridge_secondary_bus_reset(dev);
pci_printk(KERN_DEBUG, dev, "downstream link has been reset\n"); pci_printk(KERN_DEBUG, dev, "downstream link has been reset\n");
return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; return rc ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
} }

1
include/linux/pci.h
View File

@@ -1103,7 +1103,6 @@ int pci_reset_bus(struct pci_bus *bus);
int pci_try_reset_bus(struct pci_bus *bus); int pci_try_reset_bus(struct pci_bus *bus);
void pci_reset_secondary_bus(struct pci_dev *dev); void pci_reset_secondary_bus(struct pci_dev *dev);
void pcibios_reset_secondary_bus(struct pci_dev *dev); void pcibios_reset_secondary_bus(struct pci_dev *dev);
int pci_reset_bridge_secondary_bus(struct pci_dev *dev);
void pci_update_resource(struct pci_dev *dev, int resno); void pci_update_resource(struct pci_dev *dev, int resno);
int __must_check pci_assign_resource(struct pci_dev *dev, int i); int __must_check pci_assign_resource(struct pci_dev *dev, int i);
int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);