net: sh_eth: CPU dependency code collect to "struct sh_eth_cpu_data"
This improves readability by collecting CPU dependency code. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yoshihiro Shimoda
zatwierdzone przez
David S. Miller
David S. Miller
rodzic
862df49750
commit
380af9e390
@@ -2,7 +2,7 @@
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* SuperH Ethernet device driver
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*
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* Copyright (C) 2006-2008 Nobuhiro Iwamatsu
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008-2009 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@@ -39,12 +39,10 @@
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#define ETHERSMALL 60
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#define PKT_BUF_SZ 1538
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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#define SH7763_SKB_ALIGN 32
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#if defined(CONFIG_CPU_SUBTYPE_SH7763)
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/* Chip Base Address */
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# define SH_TSU_ADDR 0xFEE01800
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# define ARSTR SH_TSU_ADDR
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# define ARSTR SH_TSU_ADDR
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/* Chip Registers */
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/* E-DMAC */
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@@ -143,8 +141,8 @@
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# define FWNLCR1 0xB0
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# define FWALCR1 0x40
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#else /* CONFIG_CPU_SUBTYPE_SH7763 */
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# define RX_OFFSET 2 /* skb offset */
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#else /* #elif defined(CONFIG_CPU_SUBTYPE_SH7763) */
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/* This section is SH3 or SH2 */
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#ifndef CONFIG_CPU_SUBTYPE_SH7619
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/* Chip base address */
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# define SH_TSU_ADDR 0xA7000804
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@@ -243,6 +241,30 @@
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#endif /* CONFIG_CPU_SUBTYPE_SH7763 */
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/* There are avoid compile error... */
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#if !defined(BCULR)
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#define BCULR 0x0fc
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#endif
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#if !defined(TRIMD)
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#define TRIMD 0x0fc
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#endif
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#if !defined(APR)
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#define APR 0x0fc
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#endif
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#if !defined(MPR)
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#define MPR 0x0fc
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#endif
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#if !defined(TPAUSER)
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#define TPAUSER 0x0fc
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#endif
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/* Driver's parameters */
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#if defined(CONFIG_CPU_SH4)
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#define SH4_SKB_RX_ALIGN 32
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#else
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#define SH2_SH3_SKB_RX_ALIGN 2
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#endif
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/*
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* Register's bits
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*/
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@@ -261,11 +283,10 @@ enum GECMR_BIT {
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/* EDMR */
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enum DMAC_M_BIT {
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EDMR_EL = 0x40, /* Litte endian */
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EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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EDMR_SRST = 0x03,
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EMDR_DESC_R = 0x30, /* Descriptor reserve size */
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EDMR_EL = 0x40, /* Litte endian */
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EDMR_SRST = 0x03,
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#else /* CONFIG_CPU_SUBTYPE_SH7763 */
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EDMR_SRST = 0x01,
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#endif
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@@ -307,47 +328,43 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
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/* EESR */
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enum EESR_BIT {
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#ifndef CONFIG_CPU_SUBTYPE_SH7763
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EESR_TWB = 0x40000000,
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#else
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EESR_TWB = 0xC0000000,
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EESR_TC1 = 0x20000000,
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EESR_TUC = 0x10000000,
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EESR_ROC = 0x80000000,
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#endif
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EESR_TABT = 0x04000000,
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EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
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#ifndef CONFIG_CPU_SUBTYPE_SH7763
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EESR_ADE = 0x00800000,
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#endif
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EESR_ECI = 0x00400000,
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EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
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EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
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EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
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#ifndef CONFIG_CPU_SUBTYPE_SH7763
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EESR_CND = 0x00000800,
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#endif
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EESR_DLC = 0x00000400,
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EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
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EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
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EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
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EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
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EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
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EESR_TWB1 = 0x80000000,
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EESR_TWB = 0x40000000, /* same as TWB0 */
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EESR_TC1 = 0x20000000,
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EESR_TUC = 0x10000000,
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EESR_ROC = 0x08000000,
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EESR_TABT = 0x04000000,
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EESR_RABT = 0x02000000,
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EESR_RFRMER = 0x01000000, /* same as RFCOF */
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EESR_ADE = 0x00800000,
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EESR_ECI = 0x00400000,
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EESR_FTC = 0x00200000, /* same as TC or TC0 */
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EESR_TDE = 0x00100000,
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EESR_TFE = 0x00080000, /* same as TFUF */
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EESR_FRC = 0x00040000, /* same as FR */
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EESR_RDE = 0x00020000,
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EESR_RFE = 0x00010000,
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EESR_CND = 0x00000800,
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EESR_DLC = 0x00000400,
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EESR_CD = 0x00000200,
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EESR_RTO = 0x00000100,
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EESR_RMAF = 0x00000080,
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EESR_CEEF = 0x00000040,
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EESR_CELF = 0x00000020,
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EESR_RRF = 0x00000010,
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EESR_RTLF = 0x00000008,
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EESR_RTSF = 0x00000004,
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EESR_PRE = 0x00000002,
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EESR_CERF = 0x00000001,
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};
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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# define TX_CHECK (EESR_TC1 | EESR_FTC)
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# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
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| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
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# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
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#else
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# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
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# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
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| EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
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# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
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#endif
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#define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
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EESR_RTO)
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#define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | \
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EESR_RDE | EESR_RFRMER | EESR_ADE | \
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EESR_TFE | EESR_TDE | EESR_ECI)
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#define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
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EESR_TFE)
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/* EESIPR */
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enum DMAC_IM_BIT {
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@@ -386,12 +403,8 @@ enum FCFTR_BIT {
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FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
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FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
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};
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#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
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#ifndef CONFIG_CPU_SUBTYPE_SH7619
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#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
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#else
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#define FIFO_F_D_RFD (FCFTR_RFD0)
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#endif
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#define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
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#define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
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/* Transfer descriptor bit */
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enum TD_STS_BIT {
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@@ -404,60 +417,38 @@ enum TD_STS_BIT {
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#define TD_TFP (TD_TFP1|TD_TFP0)
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/* RMCR */
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enum RECV_RST_BIT { RMCR_RST = 0x01, };
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#define DEFAULT_RMCR_VALUE 0x00000000
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/* ECMR */
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enum FELIC_MODE_BIT {
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
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ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
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#endif
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ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
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ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
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ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
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ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
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ECMR_PRM = 0x00000001,
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ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
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ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
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};
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF |\
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ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
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#elif CONFIG_CPU_SUBTYPE_SH7619
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#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
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#else
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#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
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#endif
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/* ECSR */
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enum ECSR_STATUS_BIT {
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#ifndef CONFIG_CPU_SUBTYPE_SH7763
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ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
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#endif
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ECSR_LCHNG = 0x04,
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ECSR_MPD = 0x02, ECSR_ICD = 0x01,
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};
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
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#else
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# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
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ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
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#endif
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#define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
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ECSR_ICD | ECSIPR_MPDIP)
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/* ECSIPR */
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enum ECSIPR_STATUS_MASK_BIT {
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#ifndef CONFIG_CPU_SUBTYPE_SH7763
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ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
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#endif
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ECSIPR_LCHNGIP = 0x04,
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ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
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};
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
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#else
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# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
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ECSIPR_ICDIP | ECSIPR_MPDIP)
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#endif
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#define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
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ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
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/* APR */
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enum APR_BIT {
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@@ -483,23 +474,12 @@ enum RPADIR_BIT {
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RPADIR_PADR = 0x0003f,
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};
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#if defined(CONFIG_CPU_SUBTYPE_SH7763)
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# define RPADIR_INIT (0x00)
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#else
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# define RPADIR_INIT (RPADIR_PADS1)
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#endif
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/* RFLR */
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#define RFLR_VALUE 0x1000
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/* FDR */
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enum FIFO_SIZE_BIT {
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#ifndef CONFIG_CPU_SUBTYPE_SH7619
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FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
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#else
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FIFO_SIZE_T = 0x00000100, FIFO_SIZE_R = 0x00000001,
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#endif
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};
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#define DEFAULT_FDR_INIT 0x00000707
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enum phy_offsets {
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PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
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PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
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@@ -633,7 +613,43 @@ struct sh_eth_rxdesc {
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u32 pad0; /* padding data */
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} __attribute__((aligned(2), packed));
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/* This structure is used by each CPU dependency handling. */
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struct sh_eth_cpu_data {
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/* optional functions */
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void (*chip_reset)(struct net_device *ndev);
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void (*set_duplex)(struct net_device *ndev);
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void (*set_rate)(struct net_device *ndev);
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/* mandatory initialize value */
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unsigned long eesipr_value;
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/* optional initialize value */
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unsigned long ecsr_value;
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unsigned long ecsipr_value;
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unsigned long fdr_value;
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unsigned long fcftr_value;
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unsigned long rpadir_value;
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unsigned long rmcr_value;
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/* interrupt checking mask */
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unsigned long tx_check;
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unsigned long eesr_err_check;
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unsigned long tx_error_check;
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/* hardware features */
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unsigned no_psr:1; /* EtherC DO NOT have PSR */
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unsigned apr:1; /* EtherC have APR */
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unsigned mpr:1; /* EtherC have MPR */
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unsigned tpauser:1; /* EtherC have TPAUSER */
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unsigned bculr:1; /* EtherC have BCULR */
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unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */
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unsigned rpadir:1; /* E-DMAC have RPADIR */
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unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
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unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
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};
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struct sh_eth_private {
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struct sh_eth_cpu_data *cd;
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dma_addr_t rx_desc_dma;
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dma_addr_t tx_desc_dma;
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struct sh_eth_rxdesc *rx_ring;
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@@ -661,11 +677,7 @@ struct sh_eth_private {
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struct net_device_stats tsu_stats; /* TSU forward status */
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};
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#ifdef CONFIG_CPU_SUBTYPE_SH7763
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/* SH7763 has endian control register */
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#define swaps(x, y)
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#else
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static void swaps(char *src, int len)
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static inline void sh_eth_soft_swap(char *src, int len)
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{
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#ifdef __LITTLE_ENDIAN__
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u32 *p = (u32 *)src;
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@@ -676,5 +688,5 @@ static void swaps(char *src, int len)
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*p = swab32(*p);
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#endif
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}
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#endif /* CONFIG_CPU_SUBTYPE_SH7763 */
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#endif
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#endif /* #ifndef __SH_ETH_H__ */
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