USB: EHCI: split ehci_qh into hw and sw parts
The ehci_qh structure merged hw and sw together which is not good: 1. More and more items are being added into ehci_qh, the ehci_qh software part are unnecessary to be allocated in DMA qh_pool. 2. If HCD has local SRAM, the sw part will consume it too, and it won't bring any benefit. 3. For non-cache-coherence system, the entire ehci_qh is uncachable, actually we only need the hw part to be uncacheable. Spliting them will let the sw part to be cacheable. Signed-off-by: Alek Du <alek.du@intel.com> Cc: David Brownell <dbrownell@users.sourceforge.net> CC: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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committed by
Greg Kroah-Hartman

parent
403dbd3673
commit
3807e26d69
@@ -507,6 +507,7 @@ static int ehci_init(struct usb_hcd *hcd)
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u32 temp;
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int retval;
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u32 hcc_params;
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struct ehci_qh_hw *hw;
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spin_lock_init(&ehci->lock);
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@@ -550,12 +551,13 @@ static int ehci_init(struct usb_hcd *hcd)
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* from automatically advancing to the next td after short reads.
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*/
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ehci->async->qh_next.qh = NULL;
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ehci->async->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
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ehci->async->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
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ehci->async->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
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ehci->async->hw_qtd_next = EHCI_LIST_END(ehci);
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hw = ehci->async->hw;
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hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
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hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
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hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
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hw->hw_qtd_next = EHCI_LIST_END(ehci);
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ehci->async->qh_state = QH_STATE_LINKED;
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ehci->async->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
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hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
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/* clear interrupt enables, set irq latency */
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if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
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@@ -985,7 +987,7 @@ rescan:
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/* endpoints can be iso streams. for now, we don't
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* accelerate iso completions ... so spin a while.
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*/
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if (qh->hw_info1 == 0) {
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if (qh->hw->hw_info1 == 0) {
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ehci_vdbg (ehci, "iso delay\n");
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goto idle_timeout;
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}
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