Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto updates from Herbert Xu: "Here is the crypto update for 4.15: API: - Disambiguate EBUSY when queueing crypto request by adding ENOSPC. This change touches code outside the crypto API. - Reset settings when empty string is written to rng_current. Algorithms: - Add OSCCA SM3 secure hash. Drivers: - Remove old mv_cesa driver (replaced by marvell/cesa). - Enable rfc3686/ecb/cfb/ofb AES in crypto4xx. - Add ccm/gcm AES in crypto4xx. - Add support for BCM7278 in iproc-rng200. - Add hash support on Exynos in s5p-sss. - Fix fallback-induced error in vmx. - Fix output IV in atmel-aes. - Fix empty GCM hash in mediatek. Others: - Fix DoS potential in lib/mpi. - Fix potential out-of-order issues with padata" * 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (162 commits) lib/mpi: call cond_resched() from mpi_powm() loop crypto: stm32/hash - Fix return issue on update crypto: dh - Remove pointless checks for NULL 'p' and 'g' crypto: qat - Clean up error handling in qat_dh_set_secret() crypto: dh - Don't permit 'key' or 'g' size longer than 'p' crypto: dh - Don't permit 'p' to be 0 crypto: dh - Fix double free of ctx->p hwrng: iproc-rng200 - Add support for BCM7278 dt-bindings: rng: Document BCM7278 RNG200 compatible crypto: chcr - Replace _manual_ swap with swap macro crypto: marvell - Add a NULL entry at the end of mv_cesa_plat_id_table[] hwrng: virtio - Virtio RNG devices need to be re-registered after suspend/resume crypto: atmel - remove empty functions crypto: ecdh - remove empty exit() MAINTAINERS: update maintainer for qat crypto: caam - remove unused param of ctx_map_to_sec4_sg() crypto: caam - remove unneeded edesc zeroization crypto: atmel-aes - Reset the controller before each use crypto: atmel-aes - properly set IV after {en,de}crypt hwrng: core - Reset user selected rng by writing "" to rng_current ...
This commit is contained in:
@@ -992,7 +992,7 @@ static void init_gcm_job(struct aead_request *req,
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struct caam_ctx *ctx = crypto_aead_ctx(aead);
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unsigned int ivsize = crypto_aead_ivsize(aead);
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u32 *desc = edesc->hw_desc;
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bool generic_gcm = (ivsize == 12);
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bool generic_gcm = (ivsize == GCM_AES_IV_SIZE);
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unsigned int last;
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init_aead_job(req, edesc, all_contig, encrypt);
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@@ -1004,7 +1004,7 @@ static void init_gcm_job(struct aead_request *req,
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/* Read GCM IV */
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append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE |
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FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | 12 | last);
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FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | GCM_AES_IV_SIZE | last);
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/* Append Salt */
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if (!generic_gcm)
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append_data(desc, ctx->key + ctx->cdata.keylen, 4);
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@@ -1953,7 +1953,7 @@ static struct caam_aead_alg driver_aeads[] = {
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.setauthsize = rfc4106_setauthsize,
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.encrypt = ipsec_gcm_encrypt,
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.decrypt = ipsec_gcm_decrypt,
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.ivsize = 8,
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.ivsize = GCM_RFC4106_IV_SIZE,
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.maxauthsize = AES_BLOCK_SIZE,
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},
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.caam = {
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@@ -1971,7 +1971,7 @@ static struct caam_aead_alg driver_aeads[] = {
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.setauthsize = rfc4543_setauthsize,
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.encrypt = ipsec_gcm_encrypt,
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.decrypt = ipsec_gcm_decrypt,
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.ivsize = 8,
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.ivsize = GCM_RFC4543_IV_SIZE,
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.maxauthsize = AES_BLOCK_SIZE,
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},
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.caam = {
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@@ -1990,7 +1990,7 @@ static struct caam_aead_alg driver_aeads[] = {
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.setauthsize = gcm_setauthsize,
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.encrypt = gcm_encrypt,
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.decrypt = gcm_decrypt,
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.ivsize = 12,
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.ivsize = GCM_AES_IV_SIZE,
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.maxauthsize = AES_BLOCK_SIZE,
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},
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.caam = {
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@@ -7,7 +7,7 @@
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*/
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#include "compat.h"
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#include "ctrl.h"
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#include "regs.h"
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#include "intern.h"
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#include "desc_constr.h"
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@@ -2312,6 +2312,11 @@ static int __init caam_qi_algapi_init(void)
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if (!priv || !priv->qi_present)
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return -ENODEV;
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if (caam_dpaa2) {
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dev_info(ctrldev, "caam/qi frontend driver not suitable for DPAA 2.x, aborting...\n");
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return -ENODEV;
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}
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INIT_LIST_HEAD(&alg_list);
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/*
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@@ -218,7 +218,7 @@ static inline int buf_map_to_sec4_sg(struct device *jrdev,
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}
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/* Map state->caam_ctx, and add it to link table */
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static inline int ctx_map_to_sec4_sg(u32 *desc, struct device *jrdev,
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static inline int ctx_map_to_sec4_sg(struct device *jrdev,
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struct caam_hash_state *state, int ctx_len,
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struct sec4_sg_entry *sec4_sg, u32 flag)
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{
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@@ -773,7 +773,7 @@ static int ahash_update_ctx(struct ahash_request *req)
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edesc->src_nents = src_nents;
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edesc->sec4_sg_bytes = sec4_sg_bytes;
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ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
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ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len,
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edesc->sec4_sg, DMA_BIDIRECTIONAL);
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if (ret)
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goto unmap_ctx;
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@@ -871,9 +871,8 @@ static int ahash_final_ctx(struct ahash_request *req)
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desc = edesc->hw_desc;
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edesc->sec4_sg_bytes = sec4_sg_bytes;
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edesc->src_nents = 0;
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ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
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ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len,
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edesc->sec4_sg, DMA_TO_DEVICE);
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if (ret)
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goto unmap_ctx;
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@@ -967,7 +966,7 @@ static int ahash_finup_ctx(struct ahash_request *req)
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edesc->src_nents = src_nents;
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ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
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ret = ctx_map_to_sec4_sg(jrdev, state, ctx->ctx_len,
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edesc->sec4_sg, DMA_TO_DEVICE);
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if (ret)
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goto unmap_ctx;
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@@ -1123,7 +1122,6 @@ static int ahash_final_no_ctx(struct ahash_request *req)
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dev_err(jrdev, "unable to map dst\n");
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goto unmap;
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}
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edesc->src_nents = 0;
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#ifdef DEBUG
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print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
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@@ -1205,7 +1203,6 @@ static int ahash_update_no_ctx(struct ahash_request *req)
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edesc->src_nents = src_nents;
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edesc->sec4_sg_bytes = sec4_sg_bytes;
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edesc->dst_dma = 0;
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ret = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, state);
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if (ret)
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@@ -1417,7 +1414,6 @@ static int ahash_update_first(struct ahash_request *req)
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}
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edesc->src_nents = src_nents;
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edesc->dst_dma = 0;
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ret = ahash_edesc_add_src(ctx, edesc, req, mapped_nents, 0, 0,
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to_hash);
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@@ -32,6 +32,7 @@
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#include <crypto/aes.h>
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#include <crypto/ctr.h>
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#include <crypto/des.h>
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#include <crypto/gcm.h>
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#include <crypto/sha.h>
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#include <crypto/md5.h>
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#include <crypto/internal/aead.h>
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@@ -1440,7 +1440,7 @@
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#define MATH_SRC1_REG2 (0x02 << MATH_SRC1_SHIFT)
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#define MATH_SRC1_REG3 (0x03 << MATH_SRC1_SHIFT)
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#define MATH_SRC1_IMM (0x04 << MATH_SRC1_SHIFT)
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#define MATH_SRC1_DPOVRD (0x07 << MATH_SRC0_SHIFT)
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#define MATH_SRC1_DPOVRD (0x07 << MATH_SRC1_SHIFT)
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#define MATH_SRC1_INFIFO (0x0a << MATH_SRC1_SHIFT)
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#define MATH_SRC1_OUTFIFO (0x0b << MATH_SRC1_SHIFT)
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#define MATH_SRC1_ONE (0x0c << MATH_SRC1_SHIFT)
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