drm/i915/icl: update ddb entry start/end mask during hw ddb readout
Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to 11 bits. This patch make changes to use proper mask for ICL+ during hardware ddb value readout. Changes since V1: - Use _MASK & _SHIFT macro (James) Changes since V2: - use kernel type u8 instead of uint8_t Changes since V3: - Rebase Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180426142517.16643-4-mahesh1.kumar@intel.com
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committed by
Rodrigo Vivi

parent
aa9664ffe8
commit
37cde11ba7
@@ -3864,10 +3864,18 @@ static unsigned int skl_cursor_allocation(int num_active)
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return 8;
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}
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static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
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static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
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struct skl_ddb_entry *entry, u32 reg)
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{
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entry->start = reg & 0x3ff;
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entry->end = (reg >> 16) & 0x3ff;
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u16 mask;
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if (INTEL_GEN(dev_priv) >= 11)
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mask = ICL_DDB_ENTRY_MASK;
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else
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mask = SKL_DDB_ENTRY_MASK;
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entry->start = reg & mask;
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entry->end = (reg >> DDB_ENTRY_END_SHIFT) & mask;
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if (entry->end)
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entry->end += 1;
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}
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@@ -3884,7 +3892,8 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
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/* Cursor doesn't support NV12/planar, so no extra calculation needed */
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if (plane_id == PLANE_CURSOR) {
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val = I915_READ(CUR_BUF_CFG(pipe));
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skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
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skl_ddb_entry_init_from_hw(dev_priv,
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&ddb->plane[pipe][plane_id], val);
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return;
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}
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@@ -3903,10 +3912,13 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
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val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
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if (fourcc == DRM_FORMAT_NV12) {
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skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val2);
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skl_ddb_entry_init_from_hw(&ddb->uv_plane[pipe][plane_id], val);
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skl_ddb_entry_init_from_hw(dev_priv,
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&ddb->plane[pipe][plane_id], val2);
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skl_ddb_entry_init_from_hw(dev_priv,
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&ddb->uv_plane[pipe][plane_id], val);
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} else {
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skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
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skl_ddb_entry_init_from_hw(dev_priv,
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&ddb->plane[pipe][plane_id], val);
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}
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}
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