From e683c4b078d824ba1620477efee6be6f4ed647f9 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 23 Sep 2019 20:30:43 -0500 Subject: [PATCH 1/5] ARM: dts: arria10: Modify QSPI read_delay for Arria10 The default read delay for Arria10 QSPI module should be 3 on the Arria10 devkit. Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts index b4c0a76a4d1a..2b645642b935 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts @@ -19,7 +19,7 @@ m25p,fast-read; cdns,page-size = <256>; cdns,block-size = <16>; - cdns,read-delay = <4>; + cdns,read-delay = <3>; cdns,tshsl-ns = <50>; cdns,tsd2d-ns = <50>; cdns,tchsh-ns = <4>; From c4c8757b2d8956ae48d4d3b4acd400835c98921e Mon Sep 17 00:00:00 2001 From: "Ooi, Joyce" Date: Tue, 8 Oct 2019 01:46:39 -0700 Subject: [PATCH 2/5] arm64: dts: agilex: add QSPI support for Intel Agilex This patch adds QSPI flash interface in device tree for Intel Agilex Signed-off-by: Ooi, Joyce Signed-off-by: Dinh Nguyen --- .../boot/dts/intel/socfpga_agilex_socdk.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 7814a9e8eb08..866205ac7d51 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -73,3 +73,38 @@ &watchdog0 { status = "okay"; }; + +&qspi { + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mt25qu02g"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x034B0000>; + }; + + qspi_rootfs: partition@34B0000 { + label = "Root Filesystem - JFFS2"; + reg = <0x034B0000 0x0EB50000>; + }; + }; + }; +}; From 0c33a70b33364b19d0e2c8ce3bcdd6a95629cbf2 Mon Sep 17 00:00:00 2001 From: "Ooi, Joyce" Date: Tue, 8 Oct 2019 01:48:59 -0700 Subject: [PATCH 3/5] arm64: dts: altera: update QSPI reg addresses for Stratix10 This patch updates the reg addresses for QSPI boot and QSPI rootfs in the device tree for Stratix10 Signed-off-by: Ooi, Joyce Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 66e4ffb4e929..fb11ef05d556 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -178,12 +178,12 @@ qspi_boot: partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x4000000>; + reg = <0x0 0x034B0000>; }; qspi_rootfs: partition@4000000 { label = "Root Filesystem - JFFS2"; - reg = <0x4000000 0x4000000>; + reg = <0x034B0000 0x0EB50000>; }; }; }; From 05c9c5a99d6111f4842eacdbcad86285ebe05ced Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 18 Oct 2019 10:20:26 -0500 Subject: [PATCH 4/5] arm64: agilex: enable USB and LEDs on agilex devkit Enable USB on the Agilex devkit. Also the Agilex devkit will use the same daughter card that is used on Stratix10, thus it map the same LEDs and GPIOs. pushbutton PB_SW0 = gpio1.io4 pushbutton PB_SW1 = gpio1.io5 LED HPS_LED0 = gpio1.io20 LED HPS_LED1 = gpio1.io19 LED HPS_LED2 = gpio1.io21 Signed-off-by: Dinh Nguyen --- .../boot/dts/intel/socfpga_agilex_socdk.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 866205ac7d51..e794a12ba7c5 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -18,6 +18,24 @@ stdout-path = "serial0:115200n8"; }; + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + memory { device_type = "memory"; /* We expect the bootloader to fill in the reg */ @@ -70,6 +88,11 @@ status = "okay"; }; +&usb0 { + status = "okay"; + disable-over-current; +}; + &watchdog0 { status = "okay"; }; From aa74337ee73df5de3cb6c920100d01c3d95346cc Mon Sep 17 00:00:00 2001 From: Richard Gong Date: Thu, 17 Oct 2019 14:34:40 -0500 Subject: [PATCH 5/5] arm64: dts: agilex: add service layer, fpga manager and fpga region Add service layer, fpga manager and fpga region to the device tree on Intel Agilex platform. Signed-off-by: Richard Gong Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 36abc25320a8..94090c6fb946 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -12,6 +12,19 @@ #address-cells = <2>; #size-cells = <2>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + service_reserved: svcbuffer@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0x0 0x0 0x1000000>; + alignment = <0x1000>; + no-map; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -81,6 +94,13 @@ interrupt-parent = <&intc>; ranges = <0 0 0 0xffffffff>; + base_fpga_region { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr>; + }; + gmac0: ethernet@ff800000 { compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; reg = <0xff800000 0x2000>; @@ -442,5 +462,17 @@ status = "disabled"; }; + + firmware { + svc { + compatible = "intel,stratix10-svc"; + method = "smc"; + memory-region = <&service_reserved>; + + fpga_mgr: fpga-mgr { + compatible = "intel,stratix10-soc-fpga-mgr"; + }; + }; + }; }; };