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drm/i915: Convert intel_rc6_residency_us to ns

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Will be used for exposing the PMU counters.

v2:
 * Move intel_runtime_pm_get/put to the callers. (Chris Wilson)
 * Restore full unit conversion precision.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171121181852.16128-8-tvrtko.ursulin@linux.intel.com
This commit is contained in:
Tvrtko Ursulin
2017-11-21 18:18:51 +00:00
parent 0cd4684d6e
commit 36cc8b963f
3 changed files with 27 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/i915/i915_drv.h
View File

@@ -4228,11 +4228,17 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
const i915_reg_t reg); const i915_reg_t reg);
u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1); u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
const i915_reg_t reg)
{
return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
}
#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

9
drivers/gpu/drm/i915/i915_sysfs.c
View File

@@ -42,8 +42,13 @@ static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
static u32 calc_residency(struct drm_i915_private *dev_priv, static u32 calc_residency(struct drm_i915_private *dev_priv,
i915_reg_t reg) i915_reg_t reg)
{ {
return DIV_ROUND_CLOSEST_ULL(intel_rc6_residency_us(dev_priv, reg), u64 res;
1000);
intel_runtime_pm_get(dev_priv);
res = intel_rc6_residency_us(dev_priv, reg);
intel_runtime_pm_put(dev_priv);
return DIV_ROUND_CLOSEST_ULL(res, 1000);
} }
static ssize_t static ssize_t

27
drivers/gpu/drm/i915/intel_pm.c
View File

@@ -9437,36 +9437,35 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
return lower | (u64)upper << 8; return lower | (u64)upper << 8;
} }
u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
const i915_reg_t reg) const i915_reg_t reg)
{ {
u64 time_hw, units, div; u64 time_hw;
u32 mul, div;
if (!intel_rc6_enabled()) if (!intel_rc6_enabled())
return 0; return 0;
intel_runtime_pm_get(dev_priv);
/* On VLV and CHV, residency time is in CZ units rather than 1.28us */ /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
units = 1000; mul = 1000000;
div = dev_priv->czclk_freq; div = dev_priv->czclk_freq;
time_hw = vlv_residency_raw(dev_priv, reg); time_hw = vlv_residency_raw(dev_priv, reg);
} else if (IS_GEN9_LP(dev_priv)) {
units = 1000;
div = 1200; /* 833.33ns */
time_hw = I915_READ(reg);
} else { } else {
units = 128000; /* 1.28us */ /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
div = 100000; if (IS_GEN9_LP(dev_priv)) {
mul = 10000;
div = 12;
} else {
mul = 1280;
div = 1;
}
time_hw = I915_READ(reg); time_hw = I915_READ(reg);
} }
intel_runtime_pm_put(dev_priv); return DIV_ROUND_UP_ULL(time_hw * mul, div);
return DIV_ROUND_UP_ULL(time_hw * units, div);
} }
u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat) u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat)