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Merge branch 'drm-next-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-next

Browse Source 
This is a new pull for drm-next on top of last weeks with the following
changes:
- Fixed 64 bit divide
- Fixed vram type on vega20
- Misc vega20 fixes
- Misc DC fixes
- Fix GDS/GWS/OA domain handling

Previous changes from last week:
amdgpu/kfd:
- Picasso (new APU) support
- Raven2 (new APU) support
- Vega20 enablement
- ACP powergating improvements
- Add ABGR/XBGR display support
- VCN JPEG engine support
- Initial xGMI support
- Use load balancing for engine scheduling
- Lots of new documentation
- Rework and clean up i2c and aux handling in DC
- Add DP YCbCr 4:2:0 support in DC
- Add DMCU firmware loading for Raven (used for ABM and PSR)
- New debugfs features in DC
- LVDS support in DC
- Implement wave kill for gfx/compute (light weight reset for shaders)
- Use AGP aperture to avoid gart mappings when possible
- GPUVM performance improvements
- Bulk moves for more efficient GPUVM LRU handling
- Merge amdgpu and amdkfd into one module
- Enable gfxoff and stutter mode on Raven
- Misc cleanups

Scheduler:
- Load balancing support
- Bug fixes

ttm:
- Bulk move functionality
- Bug fixes

radeon:
- Misc cleanups

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180920150438.12693-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
2018-09-21 09:52:34 +10:00
parent 0320ac5188 846311ae68
commit 36c9c3c911
280 changed files with 81925 additions and 8278 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
drivers/gpu/drm/radeon/atombios_crtc.c
View File

@@ -1254,6 +1254,16 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
bypass_lut = true;
break;
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ABGR8888:
fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
fb_swap = (EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) |
EVERGREEN_GRPH_BLUE_CROSSBAR(EVERGREEN_GRPH_BLUE_SEL_R));
#ifdef __BIG_ENDIAN
fb_swap |= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
#endif
break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format, &format_name));
@@ -1551,6 +1561,21 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
bypass_lut = true;
break;
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ABGR8888:
fb_format =
AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
if (rdev->family >= CHIP_R600)
fb_swap =
(R600_D1GRPH_RED_CROSSBAR(R600_D1GRPH_RED_SEL_B) |
R600_D1GRPH_BLUE_CROSSBAR(R600_D1GRPH_BLUE_SEL_R));
else /* DCE1 (R5xx) */
fb_format |= AVIVO_D1GRPH_SWAP_RB;
#ifdef __BIG_ENDIAN
fb_swap |= R600_D1GRPH_SWAP_ENDIAN_32BIT;
#endif
break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format, &format_name));

2
drivers/gpu/drm/radeon/atombios_i2c.c
View File

@@ -35,7 +35,7 @@
static int radeon_process_i2c_ch(struct radeon_i2c_chan *chan,
u8 slave_addr, u8 flags,
u8 *buf, u8 num)
u8 *buf, int num)
{
struct drm_device *dev = chan->dev;
struct radeon_device *rdev = dev->dev_private;

2
drivers/gpu/drm/radeon/cik.c
View File

@@ -9600,7 +9600,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
tmp |= LC_REDO_EQ;
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
mdelay(100);
msleep(100);
/* linkctl */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);

31
drivers/gpu/drm/radeon/r600_reg.h
View File

@@ -87,11 +87,32 @@
#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
#define R600_D1GRPH_SWAP_CONTROL 0x610C
# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
#define R600_D1GRPH_SWAP_CONTROL 0x610C
# define R600_D1GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
# define R600_D1GRPH_SWAP_ENDIAN_NONE 0
# define R600_D1GRPH_SWAP_ENDIAN_16BIT 1
# define R600_D1GRPH_SWAP_ENDIAN_32BIT 2
# define R600_D1GRPH_SWAP_ENDIAN_64BIT 3
# define R600_D1GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
# define R600_D1GRPH_RED_SEL_R 0
# define R600_D1GRPH_RED_SEL_G 1
# define R600_D1GRPH_RED_SEL_B 2
# define R600_D1GRPH_RED_SEL_A 3
# define R600_D1GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
# define R600_D1GRPH_GREEN_SEL_G 0
# define R600_D1GRPH_GREEN_SEL_B 1
# define R600_D1GRPH_GREEN_SEL_A 2
# define R600_D1GRPH_GREEN_SEL_R 3
# define R600_D1GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
# define R600_D1GRPH_BLUE_SEL_B 0
# define R600_D1GRPH_BLUE_SEL_A 1
# define R600_D1GRPH_BLUE_SEL_R 2
# define R600_D1GRPH_BLUE_SEL_G 3
# define R600_D1GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
# define R600_D1GRPH_ALPHA_SEL_A 0
# define R600_D1GRPH_ALPHA_SEL_R 1
# define R600_D1GRPH_ALPHA_SEL_G 2
# define R600_D1GRPH_ALPHA_SEL_B 3
#define R600_HDP_NONSURFACE_BASE 0x2c04

4
drivers/gpu/drm/radeon/radeon_object.c
View File

@@ -421,11 +421,13 @@ int radeon_bo_unpin(struct radeon_bo *bo)
int radeon_bo_evict_vram(struct radeon_device *rdev)
{
/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
if (0 && (rdev->flags & RADEON_IS_IGP)) {
#ifndef CONFIG_HIBERNATION
if (rdev->flags & RADEON_IS_IGP) {
if (rdev->mc.igp_sideport_enabled == false)
/* Useless to evict on IGP chips */
return 0;
}
#endif
return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
}

10
drivers/gpu/drm/radeon/radeon_test.c
View File

@@ -348,7 +348,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev,
if (r)
goto out_cleanup;
mdelay(1000);
msleep(1000);
if (radeon_fence_signaled(fence1)) {
DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
@@ -369,7 +369,7 @@ void radeon_test_ring_sync(struct radeon_device *rdev,
goto out_cleanup;
}
mdelay(1000);
msleep(1000);
if (radeon_fence_signaled(fence2)) {
DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
@@ -442,7 +442,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev,
if (r)
goto out_cleanup;
mdelay(1000);
msleep(1000);
if (radeon_fence_signaled(fenceA)) {
DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
@@ -462,7 +462,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev,
radeon_ring_unlock_commit(rdev, ringC, false);
for (i = 0; i < 30; ++i) {
mdelay(100);
msleep(100);
sigA = radeon_fence_signaled(fenceA);
sigB = radeon_fence_signaled(fenceB);
if (sigA || sigB)
@@ -487,7 +487,7 @@ static void radeon_test_ring_sync2(struct radeon_device *rdev,
radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
radeon_ring_unlock_commit(rdev, ringC, false);
mdelay(1000);
msleep(1000);
r = radeon_fence_wait(fenceA, false);
if (r) {

2
drivers/gpu/drm/radeon/si.c
View File

@@ -7183,7 +7183,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
tmp |= LC_REDO_EQ;
WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
mdelay(100);
msleep(100);
/* linkctl */
pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);