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[MIPS] Fix and cleanup the mess that a dozen prom_printf variants are.

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early_printk is a so much saner thing.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2007-03-01 11:56:43 +00:00
parent ca471c8604
commit 36a885306f
42 changed files with 255 additions and 428 deletions
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124
arch/mips/mm/cerr-sb1.c
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@@ -77,66 +77,66 @@ static uint32_t extract_dc(unsigned short addr, int data);
static inline void breakout_errctl(unsigned int val)
{
if (val & CP0_ERRCTL_RECOVERABLE)
prom_printf(" recoverable");
printk(" recoverable");
if (val & CP0_ERRCTL_DCACHE)
prom_printf(" dcache");
printk(" dcache");
if (val & CP0_ERRCTL_ICACHE)
prom_printf(" icache");
printk(" icache");
if (val & CP0_ERRCTL_MULTIBUS)
prom_printf(" multiple-buserr");
prom_printf("\n");
printk(" multiple-buserr");
printk("\n");
}
static inline void breakout_cerri(unsigned int val)
{
if (val & CP0_CERRI_TAG_PARITY)
prom_printf(" tag-parity");
printk(" tag-parity");
if (val & CP0_CERRI_DATA_PARITY)
prom_printf(" data-parity");
printk(" data-parity");
if (val & CP0_CERRI_EXTERNAL)
prom_printf(" external");
prom_printf("\n");
printk(" external");
printk("\n");
}
static inline void breakout_cerrd(unsigned int val)
{
switch (val & CP0_CERRD_CAUSES) {
case CP0_CERRD_LOAD:
prom_printf(" load,");
printk(" load,");
break;
case CP0_CERRD_STORE:
prom_printf(" store,");
printk(" store,");
break;
case CP0_CERRD_FILLWB:
prom_printf(" fill/wb,");
printk(" fill/wb,");
break;
case CP0_CERRD_COHERENCY:
prom_printf(" coherency,");
printk(" coherency,");
break;
case CP0_CERRD_DUPTAG:
prom_printf(" duptags,");
printk(" duptags,");
break;
default:
prom_printf(" NO CAUSE,");
printk(" NO CAUSE,");
break;
}
if (!(val & CP0_CERRD_TYPES))
prom_printf(" NO TYPE");
printk(" NO TYPE");
else {
if (val & CP0_CERRD_MULTIPLE)
prom_printf(" multi-err");
printk(" multi-err");
if (val & CP0_CERRD_TAG_STATE)
prom_printf(" tag-state");
printk(" tag-state");
if (val & CP0_CERRD_TAG_ADDRESS)
prom_printf(" tag-address");
printk(" tag-address");
if (val & CP0_CERRD_DATA_SBE)
prom_printf(" data-SBE");
printk(" data-SBE");
if (val & CP0_CERRD_DATA_DBE)
prom_printf(" data-DBE");
printk(" data-DBE");
if (val & CP0_CERRD_EXTERNAL)
prom_printf(" external");
printk(" external");
}
prom_printf("\n");
printk("\n");
}
#ifndef CONFIG_SIBYTE_BUS_WATCHER
@@ -157,18 +157,18 @@ static void check_bus_watcher(void)
l2_tag = in64(IO_SPACE_BASE | A_L2_ECC_TAG);
#endif
memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
prom_printf("\nLast recorded signature:\n");
prom_printf("Request %02x from %d, answered by %d with Dcode %d\n",
printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
printk("\nLast recorded signature:\n");
printk("Request %02x from %d, answered by %d with Dcode %d\n",
(unsigned int)(G_SCD_BERR_TID(status) & 0x3f),
(int)(G_SCD_BERR_TID(status) >> 6),
(int)G_SCD_BERR_RID(status),
(int)G_SCD_BERR_DCODE(status));
#ifdef DUMP_L2_ECC_TAG_ON_ERROR
prom_printf("Last L2 tag w/ bad ECC: %016llx\n", l2_tag);
printk("Last L2 tag w/ bad ECC: %016llx\n", l2_tag);
#endif
} else {
prom_printf("Bus watcher indicates no error\n");
printk("Bus watcher indicates no error\n");
}
}
#else
@@ -187,11 +187,11 @@ asmlinkage void sb1_cache_error(void)
#else
csr_out32(M_SCD_TRACE_CFG_FREEZE, IO_SPACE_BASE | A_SCD_TRACE_CFG);
#endif
prom_printf("Trace buffer frozen\n");
printk("Trace buffer frozen\n");
#endif
prom_printf("Cache error exception on CPU %x:\n",
(read_c0_prid() >> 25) & 0x7);
printk("Cache error exception on CPU %x:\n",
(read_c0_prid() >> 25) & 0x7);
__asm__ __volatile__ (
" .set push\n\t"
@@ -209,43 +209,43 @@ asmlinkage void sb1_cache_error(void)
"=r" (dpahi), "=r" (dpalo), "=r" (eepc));
cerr_dpa = (((uint64_t)dpahi) << 32) | dpalo;
prom_printf(" c0_errorepc == %08x\n", eepc);
prom_printf(" c0_errctl == %08x", errctl);
printk(" c0_errorepc == %08x\n", eepc);
printk(" c0_errctl == %08x", errctl);
breakout_errctl(errctl);
if (errctl & CP0_ERRCTL_ICACHE) {
prom_printf(" c0_cerr_i == %08x", cerr_i);
printk(" c0_cerr_i == %08x", cerr_i);
breakout_cerri(cerr_i);
if (CP0_CERRI_IDX_VALID(cerr_i)) {
/* Check index of EPC, allowing for delay slot */
if (((eepc & SB1_CACHE_INDEX_MASK) != (cerr_i & SB1_CACHE_INDEX_MASK)) &&
((eepc & SB1_CACHE_INDEX_MASK) != ((cerr_i & SB1_CACHE_INDEX_MASK) - 4)))
prom_printf(" cerr_i idx doesn't match eepc\n");
printk(" cerr_i idx doesn't match eepc\n");
else {
res = extract_ic(cerr_i & SB1_CACHE_INDEX_MASK,
(cerr_i & CP0_CERRI_DATA) != 0);
if (!(res & cerr_i))
prom_printf("...didn't see indicated icache problem\n");
printk("...didn't see indicated icache problem\n");
}
}
}
if (errctl & CP0_ERRCTL_DCACHE) {
prom_printf(" c0_cerr_d == %08x", cerr_d);
printk(" c0_cerr_d == %08x", cerr_d);
breakout_cerrd(cerr_d);
if (CP0_CERRD_DPA_VALID(cerr_d)) {
prom_printf(" c0_cerr_dpa == %010llx\n", cerr_dpa);
printk(" c0_cerr_dpa == %010llx\n", cerr_dpa);
if (!CP0_CERRD_IDX_VALID(cerr_d)) {
res = extract_dc(cerr_dpa & SB1_CACHE_INDEX_MASK,
(cerr_d & CP0_CERRD_DATA) != 0);
if (!(res & cerr_d))
prom_printf("...didn't see indicated dcache problem\n");
printk("...didn't see indicated dcache problem\n");
} else {
if ((cerr_dpa & SB1_CACHE_INDEX_MASK) != (cerr_d & SB1_CACHE_INDEX_MASK))
prom_printf(" cerr_d idx doesn't match cerr_dpa\n");
printk(" cerr_d idx doesn't match cerr_dpa\n");
else {
res = extract_dc(cerr_d & SB1_CACHE_INDEX_MASK,
(cerr_d & CP0_CERRD_DATA) != 0);
if (!(res & cerr_d))
prom_printf("...didn't see indicated problem\n");
printk("...didn't see indicated problem\n");
}
}
}
@@ -334,7 +334,7 @@ static uint32_t extract_ic(unsigned short addr, int data)
uint8_t lru;
int res = 0;
prom_printf("Icache index 0x%04x ", addr);
printk("Icache index 0x%04x ", addr);
for (way = 0; way < 4; way++) {
/* Index-load-tag-I */
__asm__ __volatile__ (
@@ -354,7 +354,7 @@ static uint32_t extract_ic(unsigned short addr, int data)
taglo = ((unsigned long long)taglohi << 32) | taglolo;
if (way == 0) {
lru = (taghi >> 14) & 0xff;
prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n",
printk("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n",
((addr >> 5) & 0x3), /* bank */
((addr >> 7) & 0x3f), /* index */
(lru & 0x3),
@@ -369,19 +369,19 @@ static uint32_t extract_ic(unsigned short addr, int data)
if (valid) {
tlo_tmp = taglo & 0xfff3ff;
if (((taglo >> 10) & 1) ^ range_parity(tlo_tmp, 23, 0)) {
prom_printf(" ** bad parity in VTag0/G/ASID\n");
printk(" ** bad parity in VTag0/G/ASID\n");
res |= CP0_CERRI_TAG_PARITY;
}
if (((taglo >> 11) & 1) ^ range_parity(taglo, 63, 24)) {
prom_printf(" ** bad parity in R/VTag1\n");
printk(" ** bad parity in R/VTag1\n");
res |= CP0_CERRI_TAG_PARITY;
}
}
if (valid ^ ((taghi >> 27) & 1)) {
prom_printf(" ** bad parity for valid bit\n");
printk(" ** bad parity for valid bit\n");
res |= CP0_CERRI_TAG_PARITY;
}
prom_printf(" %d [VA %016llx] [Vld? %d] raw tags: %08X-%016llX\n",
printk(" %d [VA %016llx] [Vld? %d] raw tags: %08X-%016llX\n",
way, va, valid, taghi, taglo);
if (data) {
@@ -407,21 +407,21 @@ static uint32_t extract_ic(unsigned short addr, int data)
: "r" ((way << 13) | addr | (offset << 3)));
predecode = (datahi >> 8) & 0xff;
if (((datahi >> 16) & 1) != (uint32_t)range_parity(predecode, 7, 0)) {
prom_printf(" ** bad parity in predecode\n");
printk(" ** bad parity in predecode\n");
res |= CP0_CERRI_DATA_PARITY;
}
/* XXXKW should/could check predecode bits themselves */
if (((datahi >> 4) & 0xf) ^ inst_parity(insta)) {
prom_printf(" ** bad parity in instruction a\n");
printk(" ** bad parity in instruction a\n");
res |= CP0_CERRI_DATA_PARITY;
}
if ((datahi & 0xf) ^ inst_parity(instb)) {
prom_printf(" ** bad parity in instruction b\n");
printk(" ** bad parity in instruction b\n");
res |= CP0_CERRI_DATA_PARITY;
}
prom_printf(" %05X-%08X%08X", datahi, insta, instb);
printk(" %05X-%08X%08X", datahi, insta, instb);
}
prom_printf("\n");
printk("\n");
}
}
return res;
@@ -489,7 +489,7 @@ static uint32_t extract_dc(unsigned short addr, int data)
uint8_t ecc, lru;
int res = 0;
prom_printf("Dcache index 0x%04x ", addr);
printk("Dcache index 0x%04x ", addr);
for (way = 0; way < 4; way++) {
__asm__ __volatile__ (
" .set push\n\t"
@@ -509,7 +509,7 @@ static uint32_t extract_dc(unsigned short addr, int data)
pa = (taglo & 0xFFFFFFE000ULL) | addr;
if (way == 0) {
lru = (taghi >> 14) & 0xff;
prom_printf("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n",
printk("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n",
((addr >> 11) & 0x2) | ((addr >> 5) & 1), /* bank */
((addr >> 6) & 0x3f), /* index */
(lru & 0x3),
@@ -519,15 +519,15 @@ static uint32_t extract_dc(unsigned short addr, int data)
}
state = (taghi >> 25) & 0x1f;
valid = DC_TAG_VALID(state);
prom_printf(" %d [PA %010llx] [state %s (%02x)] raw tags: %08X-%016llX\n",
printk(" %d [PA %010llx] [state %s (%02x)] raw tags: %08X-%016llX\n",
way, pa, dc_state_str(state), state, taghi, taglo);
if (valid) {
if (((taglo >> 11) & 1) ^ range_parity(taglo, 39, 26)) {
prom_printf(" ** bad parity in PTag1\n");
printk(" ** bad parity in PTag1\n");
res |= CP0_CERRD_TAG_ADDRESS;
}
if (((taglo >> 10) & 1) ^ range_parity(taglo, 25, 13)) {
prom_printf(" ** bad parity in PTag0\n");
printk(" ** bad parity in PTag0\n");
res |= CP0_CERRD_TAG_ADDRESS;
}
} else {
@@ -567,13 +567,13 @@ static uint32_t extract_dc(unsigned short addr, int data)
}
res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE;
}
prom_printf(" %02X-%016llX", datahi, datalo);
printk(" %02X-%016llX", datahi, datalo);
}
prom_printf("\n");
printk("\n");
if (bad_ecc)
prom_printf(" dwords w/ bad ECC: %d %d %d %d\n",
!!(bad_ecc & 8), !!(bad_ecc & 4),
!!(bad_ecc & 2), !!(bad_ecc & 1));
printk(" dwords w/ bad ECC: %d %d %d %d\n",
!!(bad_ecc & 8), !!(bad_ecc & 4),
!!(bad_ecc & 2), !!(bad_ecc & 1));
}
}
return res;