MN10300: And Panasonic AM34 subarch and implement SMP
Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
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committed by
David Howells

parent
04157a6e7d
commit
368dd5acd1
@@ -58,9 +58,12 @@ void __init gdbstub_io_init(void)
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gdbstub_io_set_baud(115200);
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/* we want to get serial receive interrupts */
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set_intr_level(gdbstub_port->rx_irq, GxICR_LEVEL_0);
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set_intr_level(gdbstub_port->tx_irq, GxICR_LEVEL_0);
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set_intr_stub(EXCEP_IRQ_LEVEL0, gdbstub_io_rx_handler);
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set_intr_level(gdbstub_port->rx_irq,
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NUM2GxICR_LEVEL(CONFIG_GDBSTUB_IRQ_LEVEL));
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set_intr_level(gdbstub_port->tx_irq,
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NUM2GxICR_LEVEL(CONFIG_GDBSTUB_IRQ_LEVEL));
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set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_GDBSTUB_IRQ_LEVEL),
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gdbstub_io_rx_handler);
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*gdbstub_port->rx_icr |= GxICR_ENABLE;
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tmp = *gdbstub_port->rx_icr;
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@@ -84,12 +87,7 @@ void __init gdbstub_io_init(void)
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tmp = *gdbstub_port->_control;
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/* permit level 0 IRQs only */
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asm volatile(
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" and %0,epsw \n"
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" or %1,epsw \n"
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:
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: "i"(~EPSW_IM), "i"(EPSW_IE|EPSW_IM_1)
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);
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local_change_intr_mask_level(NUM2EPSW_IM(CONFIG_GDBSTUB_IRQ_LEVEL + 1));
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}
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/*
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@@ -184,6 +182,9 @@ int gdbstub_io_rx_char(unsigned char *_ch, int nonblock)
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{
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unsigned ix;
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u8 ch, st;
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#if defined(CONFIG_MN10300_WD_TIMER)
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int cpu;
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#endif
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*_ch = 0xff;
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@@ -201,8 +202,9 @@ try_again:
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if (nonblock)
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return -EAGAIN;
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#ifdef CONFIG_MN10300_WD_TIMER
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watchdog_alert_counter = 0;
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#endif /* CONFIG_MN10300_WD_TIMER */
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for (cpu = 0; cpu < NR_CPUS; cpu++)
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watchdog_alert_counter[cpu] = 0;
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#endif
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goto try_again;
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}
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